commit 729cb2adc9262f9f8603d9ae49959f06722f073f
author Tianyi Gou <tgou@codeaurora.org> Fri Aug 03 11:06:18 2012 -0700
committer Tianyi Gou <tgou@codeaurora.org> Fri Aug 03 12:06:43 2012 -0700
tree 4706a667bdf52700c2e706b1d8612e6c83bf40c4
parent 58f4369317c01a5b45d513c509569f85e368d42e

msm: acpuclock-8064: Update L2 frequency table

New characterization shows that L2 can run up to 1.188GHz. Therefore,
add this support.

Change-Id: I85368cf24c73bd7d868fdd803c34b18819d6ebf6
Signed-off-by: Tianyi Gou <tgou@codeaurora.org>

arch/arm/mach-msm/acpuclock-8064.c

diff --git a/arch/arm/mach-msm/acpuclock-8064.c b/arch/arm/mach-msm/acpuclock-8064.c
index 6f9960d..a9521f0 100644
--- a/arch/arm/mach-msm/acpuclock-8064.c
+++ b/arch/arm/mach-msm/acpuclock-8064.c
@@ -121,6 +121,7 @@
 	[12] = { { 1026000, HFPLL, 1, 0, 0x26 }, 1150000, 1150000, 5 },
 	[13] = { { 1080000, HFPLL, 1, 0, 0x28 }, 1150000, 1150000, 5 },
 	[14] = { { 1134000, HFPLL, 1, 0, 0x2A }, 1150000, 1150000, 5 },
+	[15] = { { 1188000, HFPLL, 1, 0, 0x2C }, 1150000, 1150000, 5 },
 };
 
 static struct acpu_level acpu_freq_tbl_slow[] __initdata = {
@@ -137,15 +138,15 @@
 	{ 1, {   918000, HFPLL, 1, 0, 0x22 }, L2(6),  1100000 },
 	{ 0, {   972000, HFPLL, 1, 0, 0x24 }, L2(6),  1125000 },
 	{ 1, {  1026000, HFPLL, 1, 0, 0x26 }, L2(6),  1125000 },
-	{ 0, {  1080000, HFPLL, 1, 0, 0x28 }, L2(14), 1175000 },
-	{ 1, {  1134000, HFPLL, 1, 0, 0x2A }, L2(14), 1175000 },
-	{ 0, {  1188000, HFPLL, 1, 0, 0x2C }, L2(14), 1200000 },
-	{ 1, {  1242000, HFPLL, 1, 0, 0x2E }, L2(14), 1200000 },
-	{ 0, {  1296000, HFPLL, 1, 0, 0x30 }, L2(14), 1225000 },
-	{ 1, {  1350000, HFPLL, 1, 0, 0x32 }, L2(14), 1225000 },
-	{ 0, {  1404000, HFPLL, 1, 0, 0x34 }, L2(14), 1237500 },
-	{ 1, {  1458000, HFPLL, 1, 0, 0x36 }, L2(14), 1237500 },
-	{ 1, {  1512000, HFPLL, 1, 0, 0x38 }, L2(14), 1250000 },
+	{ 0, {  1080000, HFPLL, 1, 0, 0x28 }, L2(15), 1175000 },
+	{ 1, {  1134000, HFPLL, 1, 0, 0x2A }, L2(15), 1175000 },
+	{ 0, {  1188000, HFPLL, 1, 0, 0x2C }, L2(15), 1200000 },
+	{ 1, {  1242000, HFPLL, 1, 0, 0x2E }, L2(15), 1200000 },
+	{ 0, {  1296000, HFPLL, 1, 0, 0x30 }, L2(15), 1225000 },
+	{ 1, {  1350000, HFPLL, 1, 0, 0x32 }, L2(15), 1225000 },
+	{ 0, {  1404000, HFPLL, 1, 0, 0x34 }, L2(15), 1237500 },
+	{ 1, {  1458000, HFPLL, 1, 0, 0x36 }, L2(15), 1237500 },
+	{ 1, {  1512000, HFPLL, 1, 0, 0x38 }, L2(15), 1250000 },
 	{ 0, { 0 } }
 };
 
@@ -163,15 +164,15 @@
 	{ 1, {   918000, HFPLL, 1, 0, 0x22 }, L2(6),  1050000 },
 	{ 0, {   972000, HFPLL, 1, 0, 0x24 }, L2(6),  1075000 },
 	{ 1, {  1026000, HFPLL, 1, 0, 0x26 }, L2(6),  1075000 },
-	{ 0, {  1080000, HFPLL, 1, 0, 0x28 }, L2(14), 1125000 },
-	{ 1, {  1134000, HFPLL, 1, 0, 0x2A }, L2(14), 1125000 },
-	{ 0, {  1188000, HFPLL, 1, 0, 0x2C }, L2(14), 1150000 },
-	{ 1, {  1242000, HFPLL, 1, 0, 0x2E }, L2(14), 1150000 },
-	{ 0, {  1296000, HFPLL, 1, 0, 0x30 }, L2(14), 1175000 },
-	{ 1, {  1350000, HFPLL, 1, 0, 0x32 }, L2(14), 1175000 },
-	{ 0, {  1404000, HFPLL, 1, 0, 0x34 }, L2(14), 1187500 },
-	{ 1, {  1458000, HFPLL, 1, 0, 0x36 }, L2(14), 1187500 },
-	{ 1, {  1512000, HFPLL, 1, 0, 0x38 }, L2(14), 1200000 },
+	{ 0, {  1080000, HFPLL, 1, 0, 0x28 }, L2(15), 1125000 },
+	{ 1, {  1134000, HFPLL, 1, 0, 0x2A }, L2(15), 1125000 },
+	{ 0, {  1188000, HFPLL, 1, 0, 0x2C }, L2(15), 1150000 },
+	{ 1, {  1242000, HFPLL, 1, 0, 0x2E }, L2(15), 1150000 },
+	{ 0, {  1296000, HFPLL, 1, 0, 0x30 }, L2(15), 1175000 },
+	{ 1, {  1350000, HFPLL, 1, 0, 0x32 }, L2(15), 1175000 },
+	{ 0, {  1404000, HFPLL, 1, 0, 0x34 }, L2(15), 1187500 },
+	{ 1, {  1458000, HFPLL, 1, 0, 0x36 }, L2(15), 1187500 },
+	{ 1, {  1512000, HFPLL, 1, 0, 0x38 }, L2(15), 1200000 },
 	{ 0, { 0 } }
 };
 
@@ -189,15 +190,15 @@
 	{ 1, {   918000, HFPLL, 1, 0, 0x22 }, L2(6),  1000000 },
 	{ 0, {   972000, HFPLL, 1, 0, 0x24 }, L2(6),  1025000 },
 	{ 1, {  1026000, HFPLL, 1, 0, 0x26 }, L2(6),  1025000 },
-	{ 0, {  1080000, HFPLL, 1, 0, 0x28 }, L2(14), 1075000 },
-	{ 1, {  1134000, HFPLL, 1, 0, 0x2A }, L2(14), 1075000 },
-	{ 0, {  1188000, HFPLL, 1, 0, 0x2C }, L2(14), 1100000 },
-	{ 1, {  1242000, HFPLL, 1, 0, 0x2E }, L2(14), 1100000 },
-	{ 0, {  1296000, HFPLL, 1, 0, 0x30 }, L2(14), 1125000 },
-	{ 1, {  1350000, HFPLL, 1, 0, 0x32 }, L2(14), 1125000 },
-	{ 0, {  1404000, HFPLL, 1, 0, 0x34 }, L2(14), 1137500 },
-	{ 1, {  1458000, HFPLL, 1, 0, 0x36 }, L2(14), 1137500 },
-	{ 1, {  1512000, HFPLL, 1, 0, 0x38 }, L2(14), 1150000 },
+	{ 0, {  1080000, HFPLL, 1, 0, 0x28 }, L2(15), 1075000 },
+	{ 1, {  1134000, HFPLL, 1, 0, 0x2A }, L2(15), 1075000 },
+	{ 0, {  1188000, HFPLL, 1, 0, 0x2C }, L2(15), 1100000 },
+	{ 1, {  1242000, HFPLL, 1, 0, 0x2E }, L2(15), 1100000 },
+	{ 0, {  1296000, HFPLL, 1, 0, 0x30 }, L2(15), 1125000 },
+	{ 1, {  1350000, HFPLL, 1, 0, 0x32 }, L2(15), 1125000 },
+	{ 0, {  1404000, HFPLL, 1, 0, 0x34 }, L2(15), 1137500 },
+	{ 1, {  1458000, HFPLL, 1, 0, 0x36 }, L2(15), 1137500 },
+	{ 1, {  1512000, HFPLL, 1, 0, 0x38 }, L2(15), 1150000 },
 	{ 0, { 0 } }
 };