)]}'
{
  "commit": "7605b3906192a171e651076325b1ed1d5ea57ec9",
  "tree": "a86d308b36fda5297349691089a868208a5a9688",
  "parents": [
    "83598f1cb06101e972b1f5aaf3408eb729622fa8"
  ],
  "author": {
    "name": "Ralf Baechle",
    "email": "ralf@linux-mips.org",
    "time": "Tue Mar 20 13:56:50 2007 +0000"
  },
  "committer": {
    "name": "Ralf Baechle",
    "email": "ralf@linux-mips.org",
    "time": "Sat Mar 24 17:01:49 2007 +0000"
  },
  "message": "[MIPS] Fix pipeline hazard.\n\nIn the the sequence:\n        ei\n        ..\n        mfc0    $x, $status\n\nthe mfc0 may not see the SR_IE bit set. This was a deliberate bug in the\nkernel code because we knew this was a safe thing to do on all R2 silicon\nso far but new silicon is changing this.\n\nSigned-off-by: Ralf Baechle \u003cralf@linux-mips.org\u003e\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "50073157a617dfcd0583bb8cfde6621285953736",
      "old_mode": 33188,
      "old_path": "include/asm-mips/hazards.h",
      "new_id": "e50c77e69cb5c11c9ef99a9253102d89d047e62f",
      "new_mode": 33188,
      "new_path": "include/asm-mips/hazards.h"
    }
  ]
}