msm: pm-8x60: Mark PC counters address as non-cacheable
The power collapse entry counters are incremented after the caches are
flushed during power collapse. In order for the counters to reflect the
current values, in the event of a crash, the counters have to be in a
non-cacheable memory.
Change-Id: If24a41cfa630fe0e843a4d41949ff38e1412889d
Signed-off-by: Mahesh Sivasubramanian <msivasub@codeaurora.org>
diff --git a/arch/arm/mach-msm/pm-8x60.c b/arch/arm/mach-msm/pm-8x60.c
index 5d2baa9..9c30e91 100644
--- a/arch/arm/mach-msm/pm-8x60.c
+++ b/arch/arm/mach-msm/pm-8x60.c
@@ -1075,7 +1075,7 @@
msm_pc_debug_counters_phys = res->start;
WARN_ON(resource_size(res) < SZ_64);
- msm_pc_debug_counters = devm_ioremap(&pdev->dev, res->start,
+ msm_pc_debug_counters = devm_ioremap_nocache(&pdev->dev, res->start,
resource_size(res));
if (!msm_pc_debug_counters)