msm: pm: Update spm retention sequence to support per core retention
On krait revision < 3, power driver is not using full spm sequence and
calling into trustzone as a part of executing krait retention.
Also krait retention is not supported on secondary cores.
krait pass3 is upgraded to use full spm sequence, hence add support
for per core retention and avoid calling into trustzone
while executing retention.
CRs-fixed: 437281
Change-Id: I6a2b3d7c4d0fd5b9a340957b16b940b7a09bbd91
Signed-off-by: Anji Jonnala <anjir@codeaurora.org>
Signed-off-by: Venkat Devarasetty <vdevaras@codeaurora.org>
diff --git a/arch/arm/mach-msm/board-8064.c b/arch/arm/mach-msm/board-8064.c
index 7fef77c..48e3a3c 100644
--- a/arch/arm/mach-msm/board-8064.c
+++ b/arch/arm/mach-msm/board-8064.c
@@ -2089,6 +2089,13 @@
0x0B, 0x00, 0x0f,
};
+static uint8_t spm_retention_with_krait_v3_cmd_sequence[] __initdata = {
+ 0x42, 0x1B, 0x00,
+ 0x05, 0x03, 0x0D, 0x0B,
+ 0x00, 0x42, 0x1B,
+ 0x0f,
+};
+
static uint8_t spm_power_collapse_with_rpm[] __initdata = {
0x00, 0x24, 0x54, 0x10,
0x09, 0x07, 0x01, 0x0B,
@@ -2140,11 +2147,16 @@
.cmd = spm_wfi_cmd_sequence,
},
[1] = {
+ .mode = MSM_SPM_MODE_POWER_RETENTION,
+ .notify_rpm = false,
+ .cmd = spm_retention_cmd_sequence,
+ },
+ [2] = {
.mode = MSM_SPM_MODE_POWER_COLLAPSE,
.notify_rpm = false,
.cmd = spm_power_collapse_without_rpm,
},
- [2] = {
+ [3] = {
.mode = MSM_SPM_MODE_POWER_COLLAPSE,
.notify_rpm = true,
.cmd = spm_power_collapse_with_rpm,
@@ -2224,9 +2236,9 @@
.reg_init_values[MSM_SPM_REG_SAW2_AVS_HYSTERESIS] = 0x00,
#endif
.reg_init_values[MSM_SPM_REG_SAW2_SPM_CTL] = 0x01,
- .reg_init_values[MSM_SPM_REG_SAW2_PMIC_DLY] = 0x02020204,
- .reg_init_values[MSM_SPM_REG_SAW2_PMIC_DATA_0] = 0x0060009C,
- .reg_init_values[MSM_SPM_REG_SAW2_PMIC_DATA_1] = 0x0000001C,
+ .reg_init_values[MSM_SPM_REG_SAW2_PMIC_DLY] = 0x03020004,
+ .reg_init_values[MSM_SPM_REG_SAW2_PMIC_DATA_0] = 0x0084009C,
+ .reg_init_values[MSM_SPM_REG_SAW2_PMIC_DATA_1] = 0x00A4001C,
.vctl_timeout_us = 50,
.num_modes = ARRAY_SIZE(msm_spm_nonboot_cpu_seq_list),
.modes = msm_spm_nonboot_cpu_seq_list,
@@ -2239,9 +2251,9 @@
.reg_init_values[MSM_SPM_REG_SAW2_AVS_HYSTERESIS] = 0x00,
#endif
.reg_init_values[MSM_SPM_REG_SAW2_SPM_CTL] = 0x01,
- .reg_init_values[MSM_SPM_REG_SAW2_PMIC_DLY] = 0x02020204,
- .reg_init_values[MSM_SPM_REG_SAW2_PMIC_DATA_0] = 0x0060009C,
- .reg_init_values[MSM_SPM_REG_SAW2_PMIC_DATA_1] = 0x0000001C,
+ .reg_init_values[MSM_SPM_REG_SAW2_PMIC_DLY] = 0x03020004,
+ .reg_init_values[MSM_SPM_REG_SAW2_PMIC_DATA_0] = 0x0084009C,
+ .reg_init_values[MSM_SPM_REG_SAW2_PMIC_DATA_1] = 0x00A4001C,
.vctl_timeout_us = 50,
.num_modes = ARRAY_SIZE(msm_spm_nonboot_cpu_seq_list),
.modes = msm_spm_nonboot_cpu_seq_list,
@@ -2254,9 +2266,9 @@
.reg_init_values[MSM_SPM_REG_SAW2_AVS_HYSTERESIS] = 0x00,
#endif
.reg_init_values[MSM_SPM_REG_SAW2_SPM_CTL] = 0x01,
- .reg_init_values[MSM_SPM_REG_SAW2_PMIC_DLY] = 0x02020204,
- .reg_init_values[MSM_SPM_REG_SAW2_PMIC_DATA_0] = 0x0060009C,
- .reg_init_values[MSM_SPM_REG_SAW2_PMIC_DATA_1] = 0x0000001C,
+ .reg_init_values[MSM_SPM_REG_SAW2_PMIC_DLY] = 0x03020004,
+ .reg_init_values[MSM_SPM_REG_SAW2_PMIC_DATA_0] = 0x0084009C,
+ .reg_init_values[MSM_SPM_REG_SAW2_PMIC_DATA_1] = 0x00A4001C,
.vctl_timeout_us = 50,
.num_modes = ARRAY_SIZE(msm_spm_nonboot_cpu_seq_list),
.modes = msm_spm_nonboot_cpu_seq_list,
@@ -3231,6 +3243,23 @@
static struct msm_serial_hs_platform_data apq8064_uartdm_gsbi4_pdata;
#endif
+static void __init apq8064ab_update_retention_spm(void)
+{
+ int i;
+
+ /* Update the SPM sequences for krait retention on all cores */
+ for (i = 0; i < ARRAY_SIZE(msm_spm_data); i++) {
+ int j;
+ struct msm_spm_platform_data *pdata = &msm_spm_data[i];
+ for (j = 0; j < pdata->num_modes; j++) {
+ if (pdata->modes[j].cmd ==
+ spm_retention_cmd_sequence)
+ pdata->modes[j].cmd =
+ spm_retention_with_krait_v3_cmd_sequence;
+ }
+ }
+}
+
static void __init apq8064_common_init(void)
{
u32 platform_version = socinfo_get_platform_version();
@@ -3346,11 +3375,16 @@
}
if (cpu_is_apq8064ab())
apq8064ab_update_krait_spm();
+ if (cpu_is_krait_v3()) {
+ msm_pm_set_tz_retention_flag(0);
+ apq8064ab_update_retention_spm();
+ } else {
+ msm_pm_set_tz_retention_flag(1);
+ }
msm_spm_init(msm_spm_data, ARRAY_SIZE(msm_spm_data));
msm_spm_l2_init(msm_spm_l2_data);
BUG_ON(msm_pm_boot_init(&msm_pm_boot_pdata));
apq8064_epm_adc_init();
- msm_pm_set_tz_retention_flag(1);
}
static void __init apq8064_allocate_memory_regions(void)
diff --git a/arch/arm/mach-msm/board-8930.c b/arch/arm/mach-msm/board-8930.c
index 7b50028..5a373ab 100644
--- a/arch/arm/mach-msm/board-8930.c
+++ b/arch/arm/mach-msm/board-8930.c
@@ -1646,11 +1646,18 @@
0x03, 0x0f,
};
+
static uint8_t spm_retention_cmd_sequence[] __initdata = {
0x00, 0x05, 0x03, 0x0D,
0x0B, 0x00, 0x0f,
};
+static uint8_t spm_retention_with_krait_v3_cmd_sequence[] __initdata = {
+ 0x42, 0x1B, 0x00,
+ 0x05, 0x03, 0x0D, 0x0B,
+ 0x00, 0x42, 0x1B,
+ 0x0f,
+};
static uint8_t spm_power_collapse_without_rpm[] __initdata = {
0x00, 0x24, 0x54, 0x10,
0x09, 0x03, 0x01,
@@ -1695,11 +1702,16 @@
.cmd = spm_wfi_cmd_sequence,
},
[1] = {
+ .mode = MSM_SPM_MODE_POWER_RETENTION,
+ .notify_rpm = false,
+ .cmd = spm_retention_cmd_sequence,
+ },
+ [2] = {
.mode = MSM_SPM_MODE_POWER_COLLAPSE,
.notify_rpm = false,
.cmd = spm_power_collapse_without_rpm,
},
- [2] = {
+ [3] = {
.mode = MSM_SPM_MODE_POWER_COLLAPSE,
.notify_rpm = true,
.cmd = spm_power_collapse_with_rpm,
@@ -1730,9 +1742,9 @@
.reg_init_values[MSM_SPM_REG_SAW2_AVS_HYSTERESIS] = 0x00,
#endif
.reg_init_values[MSM_SPM_REG_SAW2_SPM_CTL] = 0x01,
- .reg_init_values[MSM_SPM_REG_SAW2_PMIC_DLY] = 0x02020204,
- .reg_init_values[MSM_SPM_REG_SAW2_PMIC_DATA_0] = 0x0060009C,
- .reg_init_values[MSM_SPM_REG_SAW2_PMIC_DATA_1] = 0x0000001C,
+ .reg_init_values[MSM_SPM_REG_SAW2_PMIC_DLY] = 0x03020004,
+ .reg_init_values[MSM_SPM_REG_SAW2_PMIC_DATA_0] = 0x0084009C,
+ .reg_init_values[MSM_SPM_REG_SAW2_PMIC_DATA_1] = 0x00A4001C,
.vctl_timeout_us = 50,
.num_modes = ARRAY_SIZE(msm_spm_nonboot_cpu_seq_list),
.modes = msm_spm_nonboot_cpu_seq_list,
@@ -2849,6 +2861,23 @@
pdata->uses_pm8917 = true;
}
+static void __init msm8930ab_update_retention_spm(void)
+{
+ int i;
+
+ /* Update the SPM sequences for krait retention on all cores */
+ for (i = 0; i < ARRAY_SIZE(msm_spm_data); i++) {
+ int j;
+ struct msm_spm_platform_data *pdata = &msm_spm_data[i];
+ for (j = 0; j < pdata->num_modes; j++) {
+ if (pdata->modes[j].cmd ==
+ spm_retention_cmd_sequence)
+ pdata->modes[j].cmd =
+ spm_retention_with_krait_v3_cmd_sequence;
+ }
+ }
+}
+
static void __init msm8930_cdp_init(void)
{
if (socinfo_get_pmic_model() == PMIC_MODEL_PM8917)
@@ -2917,6 +2946,12 @@
#endif
msm8930_i2c_init();
msm8930_init_gpu();
+ if (cpu_is_krait_v3()) {
+ msm_pm_set_tz_retention_flag(0);
+ msm8930ab_update_retention_spm();
+ } else {
+ msm_pm_set_tz_retention_flag(1);
+ }
msm_spm_init(msm_spm_data, ARRAY_SIZE(msm_spm_data));
msm_spm_l2_init(msm_spm_l2_data);
msm8930_init_buses();
@@ -2974,7 +3009,6 @@
ARRAY_SIZE(msm_slim_devices));
change_memory_power = &msm8930_change_memory_power;
BUG_ON(msm_pm_boot_init(&msm_pm_boot_pdata));
- msm_pm_set_tz_retention_flag(1);
if (PLATFORM_IS_CHARM25())
platform_add_devices(mdm_devices, ARRAY_SIZE(mdm_devices));
diff --git a/arch/arm/mach-msm/board-8960.c b/arch/arm/mach-msm/board-8960.c
index 4b4d653..3b7fc14 100644
--- a/arch/arm/mach-msm/board-8960.c
+++ b/arch/arm/mach-msm/board-8960.c
@@ -1753,6 +1753,13 @@
0x0B, 0x00, 0x0f,
};
+static uint8_t spm_retention_with_krait_v3_cmd_sequence[] __initdata = {
+ 0x42, 0x1B, 0x00,
+ 0x05, 0x03, 0x0D, 0x0B,
+ 0x00, 0x42, 0x1B,
+ 0x0f,
+};
+
static uint8_t spm_power_collapse_without_rpm[] __initdata = {
0x00, 0x24, 0x54, 0x10,
0x09, 0x03, 0x01,
@@ -1813,12 +1820,20 @@
.notify_rpm = false,
.cmd = spm_wfi_cmd_sequence,
},
+
[1] = {
+ .mode = MSM_SPM_MODE_POWER_RETENTION,
+ .notify_rpm = false,
+ .cmd = spm_retention_cmd_sequence,
+ },
+
+ [2] = {
.mode = MSM_SPM_MODE_POWER_COLLAPSE,
.notify_rpm = false,
.cmd = spm_power_collapse_without_rpm,
},
- [2] = {
+
+ [3] = {
.mode = MSM_SPM_MODE_POWER_COLLAPSE,
.notify_rpm = true,
.cmd = spm_power_collapse_with_rpm,
@@ -1849,9 +1864,9 @@
.reg_init_values[MSM_SPM_REG_SAW2_AVS_HYSTERESIS] = 0x00020000,
#endif
.reg_init_values[MSM_SPM_REG_SAW2_SPM_CTL] = 0x01,
- .reg_init_values[MSM_SPM_REG_SAW2_PMIC_DLY] = 0x02020204,
- .reg_init_values[MSM_SPM_REG_SAW2_PMIC_DATA_0] = 0x0060009C,
- .reg_init_values[MSM_SPM_REG_SAW2_PMIC_DATA_1] = 0x0000001C,
+ .reg_init_values[MSM_SPM_REG_SAW2_PMIC_DLY] = 0x03020004,
+ .reg_init_values[MSM_SPM_REG_SAW2_PMIC_DATA_0] = 0x0084009C,
+ .reg_init_values[MSM_SPM_REG_SAW2_PMIC_DATA_1] = 0x00A4001C,
.vctl_timeout_us = 50,
.num_modes = ARRAY_SIZE(msm_spm_nonboot_cpu_seq_list),
.modes = msm_spm_nonboot_cpu_seq_list,
@@ -3397,6 +3412,23 @@
}
}
+static void __init msm8960ab_update_retention_spm(void)
+{
+ int i;
+
+ /* Update the SPM sequences for krait retention on all cores */
+ for (i = 0; i < ARRAY_SIZE(msm_spm_data); i++) {
+ int j;
+ struct msm_spm_platform_data *pdata = &msm_spm_data[i];
+ for (j = 0; j < pdata->num_modes; j++) {
+ if (pdata->modes[j].cmd ==
+ spm_retention_cmd_sequence)
+ pdata->modes[j].cmd =
+ spm_retention_with_krait_v3_cmd_sequence;
+ }
+ }
+}
+
static void __init msm8960_cdp_init(void)
{
if (meminfo_init(SYS_MEMORY, SZ_256M) < 0)
@@ -3453,6 +3485,12 @@
msm8960_gfx_init();
if (cpu_is_msm8960ab())
msm8960ab_update_krait_spm();
+ if (cpu_is_krait_v3()) {
+ msm_pm_set_tz_retention_flag(0);
+ msm8960ab_update_retention_spm();
+ } else {
+ msm_pm_set_tz_retention_flag(1);
+ }
msm_spm_init(msm_spm_data, ARRAY_SIZE(msm_spm_data));
msm_spm_l2_init(msm_spm_l2_data);
msm8960_init_buses();
@@ -3519,7 +3557,6 @@
mdm_sglte_device.dev.platform_data = &sglte_platform_data;
platform_device_register(&mdm_sglte_device);
}
- msm_pm_set_tz_retention_flag(1);
ion_adjust_secure_allocation();
}