commit 7bcf7717b6a047c272410d0cd00213185fe6b99d
author Ralf Baechle <ralf@linux-mips.org> Thu Oct 11 23:46:09 2007 +0100
committer Ralf Baechle <ralf@linux-mips.org> Thu Oct 11 23:46:09 2007 +0100
tree 81c5d6bbc2130815713e22bb5408ea80b6e1c499
parent 91a2fcc88634663e9e13dcdfad0e4a860e64aeee

[MIPS] Implement clockevents for R4000-style cp0 count/compare interrupt

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

arch/mips/au1000/common/irq.c

diff --git a/arch/mips/au1000/common/irq.c b/arch/mips/au1000/common/irq.c
index 47949d6..a6640b9 100644
--- a/arch/mips/au1000/common/irq.c
+++ b/arch/mips/au1000/common/irq.c
@@ -633,7 +633,7 @@
 	unsigned int pending = read_c0_status() & read_c0_cause() & ST0_IM;
 
 	if (pending & CAUSEF_IP7)
-		ll_timer_interrupt(63);
+		do_IRQ(63);
 	else if (pending & CAUSEF_IP2)
 		intc0_req0_irqdispatch();
 	else if (pending & CAUSEF_IP3)