)]}'
{
  "commit": "80ce3f67e75ffa14ad99b26457a7e9558b8b001a",
  "tree": "41c409c5f2bca580b3a9305307927461cab91450",
  "parents": [
    "b11a25aaeccc29d5090d1ce9776af20e3ee99ab9"
  ],
  "author": {
    "name": "Casey Leedom",
    "email": "leedom@chelsio.com",
    "time": "Mon Jan 10 13:53:43 2011 -0800"
  },
  "committer": {
    "name": "David S. Miller",
    "email": "davem@davemloft.net",
    "time": "Mon Jan 10 13:53:43 2011 -0800"
  },
  "message": "cxgb4vf: fix mailbox data/control coherency domain race\n\nFor the VFs, the Mailbox Data \"registers\" are actually backed by\nT4\u0027s \"MA\" interface rather than PL Registers (as is the case for\nthe PFs).  Because these are in different coherency domains, the\nwrite to the VF\u0027s PL-register-backed Mailbox Control can race in\nfront of the writes to the MA-backed VF Mailbox Data \"registers\".\nSo we need to do a read-back on at least one byte of the VF Mailbox\nData registers before doing the write to the VF Mailbox Control\nregister.\n\nSigned-off-by: Casey Leedom \u003cleedom@chelsio.com\u003e\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "e4bec78c8e3fbda595e9b29cde3b14908fe6ec66",
      "old_mode": 33188,
      "old_path": "drivers/net/cxgb4vf/t4vf_hw.c",
      "new_id": "0f51c80475ce4029151da4fe3e1c233ec6fad355",
      "new_mode": 33188,
      "new_path": "drivers/net/cxgb4vf/t4vf_hw.c"
    }
  ]
}