msm: clock-8960: Enable necessary regulators for hdmi_pll
Rather than requiring the display driver to enable these regulators
before enabling the clocks which use the HDMI PLL, enable these
regulators in the clock driver. The HDMI PLL is powered by the same
rail as the SR2 PLLs, so re-use that vdd_class.
Change-Id: Ieed938fc06cbd4ec7b6317b956b10d8ee7b4c578
Signed-off-by: Matt Wagantall <mattw@codeaurora.org>
diff --git a/arch/arm/mach-msm/clock-8960.c b/arch/arm/mach-msm/clock-8960.c
index c0fac12..d31e629 100644
--- a/arch/arm/mach-msm/clock-8960.c
+++ b/arch/arm/mach-msm/clock-8960.c
@@ -419,16 +419,16 @@
.fmax[VDD_DIG_##l2] = (f2), \
.fmax[VDD_DIG_##l3] = (f3)
-enum vdd_sr2_pll_levels {
- VDD_SR2_PLL_OFF,
- VDD_SR2_PLL_ON
+enum vdd_sr2_hdmi_pll_levels {
+ VDD_SR2_HDMI_PLL_OFF,
+ VDD_SR2_HDMI_PLL_ON
};
-static int set_vdd_sr2_pll_8960(struct clk_vdd_class *vdd_class, int level)
+static int set_vdd_sr2_hdmi_pll_8960(struct clk_vdd_class *vdd_class, int level)
{
int rc = 0;
- if (level == VDD_SR2_PLL_OFF) {
+ if (level == VDD_SR2_HDMI_PLL_OFF) {
rc = rpm_vreg_set_voltage(RPM_VREG_ID_PM8921_L23,
RPM_VREG_VOTER3, 0, 0, 1);
if (rc)
@@ -453,20 +453,20 @@
return rc;
}
-static DEFINE_VDD_CLASS(vdd_sr2_pll, set_vdd_sr2_pll_8960);
+static DEFINE_VDD_CLASS(vdd_sr2_hdmi_pll, set_vdd_sr2_hdmi_pll_8960);
static int sr2_lreg_uv[] = {
- [VDD_SR2_PLL_OFF] = 0,
- [VDD_SR2_PLL_ON] = 1800000,
+ [VDD_SR2_HDMI_PLL_OFF] = 0,
+ [VDD_SR2_HDMI_PLL_ON] = 1800000,
};
-static int set_vdd_sr2_pll_8064(struct clk_vdd_class *vdd_class, int level)
+static int set_vdd_sr2_hdmi_pll_8064(struct clk_vdd_class *vdd_class, int level)
{
return rpm_vreg_set_voltage(RPM_VREG_ID_PM8921_LVS7, RPM_VREG_VOTER3,
sr2_lreg_uv[level], sr2_lreg_uv[level], 1);
}
-static int set_vdd_sr2_pll_8930(struct clk_vdd_class *vdd_class, int level)
+static int set_vdd_sr2_hdmi_pll_8930(struct clk_vdd_class *vdd_class, int level)
{
return rpm_vreg_set_voltage(RPM_VREG_ID_PM8038_L23, RPM_VREG_VOTER3,
sr2_lreg_uv[level], sr2_lreg_uv[level], 1);
@@ -498,8 +498,8 @@
.dbg_name = "pll3_clk",
.rate = 1200000000,
.ops = &clk_ops_local_pll,
- .vdd_class = &vdd_sr2_pll,
- .fmax[VDD_SR2_PLL_ON] = ULONG_MAX,
+ .vdd_class = &vdd_sr2_hdmi_pll,
+ .fmax[VDD_SR2_HDMI_PLL_ON] = ULONG_MAX,
CLK_INIT(pll3_clk.c),
.warned = true,
},
@@ -3926,6 +3926,8 @@
static struct clk hdmi_pll_clk = {
.dbg_name = "hdmi_pll_clk",
.ops = &clk_ops_hdmi_pll,
+ .vdd_class = &vdd_sr2_hdmi_pll,
+ .fmax[VDD_SR2_HDMI_PLL_ON] = ULONG_MAX,
CLK_INIT(hdmi_pll_clk),
};
@@ -6258,10 +6260,10 @@
static void __init msm8960_clock_pre_init(void)
{
if (cpu_is_apq8064()) {
- vdd_sr2_pll.set_vdd = set_vdd_sr2_pll_8064;
+ vdd_sr2_hdmi_pll.set_vdd = set_vdd_sr2_hdmi_pll_8064;
} else if (cpu_is_msm8930() || cpu_is_msm8930aa() || cpu_is_msm8627()) {
vdd_dig.set_vdd = set_vdd_dig_8930;
- vdd_sr2_pll.set_vdd = set_vdd_sr2_pll_8930;
+ vdd_sr2_hdmi_pll.set_vdd = set_vdd_sr2_hdmi_pll_8930;
}
/*