)]}'
{
  "commit": "847b9dfccad7dd34b2e44b1c6ceeb1c4cb88084a",
  "tree": "46374a118b2f42c17aef00ec478021043e56e38b",
  "parents": [
    "bca70d24c09b740d6fd96b972011644cba8383d6"
  ],
  "author": {
    "name": "Chris Dearman",
    "email": "chris@mips.com",
    "time": "Mon Aug 07 15:08:01 2006 +0100"
  },
  "committer": {
    "name": "Ralf Baechle",
    "email": "ralf@linux-mips.org",
    "time": "Wed Sep 27 13:37:33 2006 +0100"
  },
  "message": "[MIPS] MT: Initialise all writable bits in Cause register to zero.\n\nRecent 34Ks come out of reset with WP enabled on VPE 1 so we take an\nimmediate exception when starting the second VPE.\n\nSigned-off-by: Chris Dearman \u003cchris@mips.com\u003e\nSigned-off-by: Ralf Baechle \u003cralf@linux-mips.org\u003e\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "93429a4d301296d2b550ce34d8f254ea93aaa8aa",
      "old_mode": 33188,
      "old_path": "arch/mips/kernel/smp-mt.c",
      "new_id": "766253c44f3fd8d3dcae954755702e13bb78506a",
      "new_mode": 33188,
      "new_path": "arch/mips/kernel/smp-mt.c"
    }
  ]
}