msm: kgsl: Remove the use of asid
Remove the use of asid(application space ID) from the kgsl driver
for IOMMU since it's known to cause to stability issues on the
2D core
Change-Id: I92f82ebb0941296c7ad625dd833822dd918fe386
CRs-fixed: 379439
Signed-off-by: Shubhraprakash Das <sadas@codeaurora.org>
diff --git a/drivers/gpu/msm/adreno.c b/drivers/gpu/msm/adreno.c
index 2f48999..fc51970 100644
--- a/drivers/gpu/msm/adreno.c
+++ b/drivers/gpu/msm/adreno.c
@@ -303,8 +303,8 @@
device->mmu.setstate_memory.gpuaddr +
KGSL_IOMMU_SETSTATE_NOP_OFFSET);
+ pt_val = kgsl_mmu_pt_get_base_addr(device->mmu.hwpagetable);
if (flags & KGSL_MMUFLAGS_PTUPDATE) {
- pt_val = kgsl_mmu_pt_get_base_addr(device->mmu.hwpagetable);
/*
* We need to perfrom the following operations for all
* IOMMU units
@@ -338,24 +338,6 @@
reg_pt_val,
device->mmu.setstate_memory.gpuaddr +
KGSL_IOMMU_SETSTATE_NOP_OFFSET);
-
- /* set the asid */
- *cmds++ = cp_type3_packet(CP_MEM_WRITE, 2);
- *cmds++ = reg_map_desc[i]->gpuaddr +
- (KGSL_IOMMU_CONTEXT_USER <<
- KGSL_IOMMU_CTX_SHIFT) + KGSL_IOMMU_CONTEXTIDR;
- *cmds++ = kgsl_mmu_get_hwpagetable_asid(&device->mmu);
- *cmds++ = cp_type3_packet(CP_WAIT_FOR_IDLE, 1);
- *cmds++ = 0x00000000;
-
- /* Read back asid to ensure above write completes */
- cmds += adreno_add_read_cmds(device, cmds,
- reg_map_desc[i]->gpuaddr +
- (KGSL_IOMMU_CONTEXT_USER <<
- KGSL_IOMMU_CTX_SHIFT) + KGSL_IOMMU_CONTEXTIDR,
- kgsl_mmu_get_hwpagetable_asid(&device->mmu),
- device->mmu.setstate_memory.gpuaddr +
- KGSL_IOMMU_SETSTATE_NOP_OFFSET);
}
/* invalidate all base pointers */
*cmds++ = cp_type3_packet(CP_INVALIDATE_STATE, 1);
@@ -367,15 +349,21 @@
}
if (flags & KGSL_MMUFLAGS_TLBFLUSH) {
/*
- * tlb flush based on asid, no need to flush entire tlb
+ * tlb flush
*/
for (i = 0; i < num_iommu_units; i++) {
+ reg_pt_val = (pt_val &
+ (KGSL_IOMMU_TTBR0_PA_MASK <<
+ KGSL_IOMMU_TTBR0_PA_SHIFT)) +
+ kgsl_mmu_get_pt_lsb(&device->mmu, i,
+ KGSL_IOMMU_CONTEXT_USER);
+
*cmds++ = cp_type3_packet(CP_MEM_WRITE, 2);
*cmds++ = (reg_map_desc[i]->gpuaddr +
(KGSL_IOMMU_CONTEXT_USER <<
KGSL_IOMMU_CTX_SHIFT) +
- KGSL_IOMMU_CTX_TLBIASID);
- *cmds++ = kgsl_mmu_get_hwpagetable_asid(&device->mmu);
+ KGSL_IOMMU_CTX_TLBIALL);
+ *cmds++ = 1;
cmds += __adreno_add_idle_indirect_cmds(cmds,
device->mmu.setstate_memory.gpuaddr +
@@ -384,9 +372,8 @@
cmds += adreno_add_read_cmds(device, cmds,
reg_map_desc[i]->gpuaddr +
(KGSL_IOMMU_CONTEXT_USER <<
- KGSL_IOMMU_CTX_SHIFT) +
- KGSL_IOMMU_CONTEXTIDR,
- kgsl_mmu_get_hwpagetable_asid(&device->mmu),
+ KGSL_IOMMU_CTX_SHIFT) + KGSL_IOMMU_TTBR0,
+ reg_pt_val,
device->mmu.setstate_memory.gpuaddr +
KGSL_IOMMU_SETSTATE_NOP_OFFSET);
}
diff --git a/drivers/gpu/msm/kgsl_gpummu.c b/drivers/gpu/msm/kgsl_gpummu.c
index 998eaab..edccff1 100644
--- a/drivers/gpu/msm/kgsl_gpummu.c
+++ b/drivers/gpu/msm/kgsl_gpummu.c
@@ -732,7 +732,6 @@
.mmu_get_current_ptbase = kgsl_gpummu_get_current_ptbase,
.mmu_enable_clk = NULL,
.mmu_disable_clk_on_ts = NULL,
- .mmu_get_hwpagetable_asid = NULL,
.mmu_get_pt_lsb = NULL,
.mmu_get_reg_map_desc = NULL,
};
diff --git a/drivers/gpu/msm/kgsl_iommu.c b/drivers/gpu/msm/kgsl_iommu.c
index 25d0463..016771b 100644
--- a/drivers/gpu/msm/kgsl_iommu.c
+++ b/drivers/gpu/msm/kgsl_iommu.c
@@ -292,14 +292,6 @@
struct kgsl_iommu_pt *iommu_pt = mmu_specific_pt;
if (iommu_pt->domain)
iommu_domain_free(iommu_pt->domain);
- if (iommu_pt->iommu) {
- if ((KGSL_IOMMU_ASID_REUSE == iommu_pt->asid) &&
- iommu_pt->iommu->asid_reuse)
- iommu_pt->iommu->asid_reuse--;
- if (!iommu_pt->iommu->asid_reuse ||
- (KGSL_IOMMU_ASID_REUSE != iommu_pt->asid))
- clear_bit(iommu_pt->asid, iommu_pt->iommu->asids);
- }
kfree(iommu_pt);
}
@@ -621,20 +613,15 @@
unsigned int context_id)
{
if (mmu->flags & KGSL_FLAGS_STARTED) {
- struct kgsl_iommu *iommu = mmu->priv;
- struct kgsl_iommu_pt *iommu_pt = pagetable->priv;
/* page table not current, then setup mmu to use new
* specified page table
*/
if (mmu->hwpagetable != pagetable) {
unsigned int flags = 0;
mmu->hwpagetable = pagetable;
- /* force tlb flush if asid is reused */
- if (iommu->asid_reuse &&
- (KGSL_IOMMU_ASID_REUSE == iommu_pt->asid))
- flags |= KGSL_MMUFLAGS_TLBFLUSH;
flags |= kgsl_mmu_pt_get_flags(mmu->hwpagetable,
- mmu->device->id);
+ mmu->device->id) |
+ KGSL_MMUFLAGS_TLBFLUSH;
kgsl_setstate(mmu, context_id,
KGSL_MMUFLAGS_PTUPDATE | flags);
}
@@ -657,14 +644,6 @@
sizeof(struct kgsl_iommu));
return -ENOMEM;
}
- iommu->asids = kzalloc(BITS_TO_LONGS(KGSL_IOMMU_MAX_ASIDS) *
- sizeof(unsigned long), GFP_KERNEL);
- if (!iommu->asids) {
- KGSL_CORE_ERR("kzalloc(%d) failed\n",
- sizeof(struct kgsl_iommu));
- status = -ENOMEM;
- goto done;
- }
mmu->priv = iommu;
status = kgsl_get_iommu_ctxt(mmu);
@@ -684,7 +663,6 @@
__func__);
done:
if (status) {
- kfree(iommu->asids);
kfree(iommu);
mmu->priv = NULL;
}
@@ -718,7 +696,6 @@
goto err;
}
iommu_pt = mmu->priv_bank_table->priv;
- iommu_pt->asid = 1;
}
mmu->defaultpagetable = kgsl_mmu_getpagetable(KGSL_MMU_GLOBAL_PT);
/* Return error if the default pagetable doesn't exist */
@@ -740,14 +717,6 @@
goto err;
}
}
- /*
- * The dafault pagetable always has asid 0 assigned by the iommu driver
- * and asid 1 is assigned to the private context.
- */
- iommu_pt = mmu->defaultpagetable->priv;
- iommu_pt->asid = 0;
- set_bit(0, iommu->asids);
- set_bit(1, iommu->asids);
return status;
err:
for (i--; i >= 0; i--) {
@@ -818,12 +787,6 @@
*/
for (i = 0; i < iommu->unit_count; i++) {
struct kgsl_iommu_unit *iommu_unit = &iommu->iommu_units[i];
- /* Make sure that the ASID of the priv bank is set to 1.
- * When we a different pagetable for the priv bank then the
- * iommu driver sets the ASID to 0 instead of 1 */
- KGSL_IOMMU_SET_IOMMU_REG(iommu->iommu_units[i].reg_map.hostptr,
- KGSL_IOMMU_CONTEXT_PRIV,
- CONTEXTIDR, 1);
for (j = 0; j < iommu_unit->dev_count; j++)
iommu_unit->dev[j].pt_lsb = KGSL_IOMMMU_PT_LSB(
KGSL_IOMMU_GET_IOMMU_REG(
@@ -831,10 +794,6 @@
iommu_unit->dev[j].ctx_id,
TTBR0));
}
- iommu->asid = KGSL_IOMMU_GET_IOMMU_REG(
- iommu->iommu_units[0].reg_map.hostptr,
- KGSL_IOMMU_CONTEXT_USER,
- CONTEXTIDR);
kgsl_iommu_disable_clk_on_ts(mmu, 0, false);
mmu->flags |= KGSL_FLAGS_STARTED;
@@ -955,7 +914,6 @@
kgsl_mmu_putpagetable(mmu->priv_bank_table);
if (mmu->defaultpagetable)
kgsl_mmu_putpagetable(mmu->defaultpagetable);
- kfree(iommu->asids);
kfree(iommu);
return 0;
@@ -981,47 +939,6 @@
}
/*
- * kgsl_iommu_get_hwpagetable_asid - Returns asid(application space ID) for a
- * pagetable
- * @mmu - Pointer to mmu structure
- *
- * Allocates an asid to a IOMMU domain if it does not already have one. asid's
- * are unique identifiers for pagetable that can be used to selectively flush
- * tlb entries of the IOMMU unit.
- * Return - asid to be used with the IOMMU domain
- */
-static int kgsl_iommu_get_hwpagetable_asid(struct kgsl_mmu *mmu)
-{
- struct kgsl_iommu *iommu = mmu->priv;
- struct kgsl_iommu_pt *iommu_pt = mmu->hwpagetable->priv;
-
- /*
- * If the iommu pagetable does not have any asid assigned and is not the
- * default pagetable then assign asid.
- */
- if (!iommu_pt->asid && iommu_pt != mmu->defaultpagetable->priv) {
- iommu_pt->asid = find_first_zero_bit(iommu->asids,
- KGSL_IOMMU_MAX_ASIDS);
- /* No free bits means reuse asid */
- if (iommu_pt->asid >= KGSL_IOMMU_MAX_ASIDS) {
- iommu_pt->asid = KGSL_IOMMU_ASID_REUSE;
- iommu->asid_reuse++;
- }
- set_bit(iommu_pt->asid, iommu->asids);
- /*
- * Store pointer to asids list so that during pagetable destroy
- * the asid assigned to this pagetable may be cleared
- */
- iommu_pt->iommu = iommu;
- }
- /* Return the asid + the constant part of asid that never changes */
- return (iommu_pt->asid & (KGSL_IOMMU_CONTEXTIDR_ASID_MASK <<
- KGSL_IOMMU_CONTEXTIDR_ASID_SHIFT)) +
- (iommu->asid & ~(KGSL_IOMMU_CONTEXTIDR_ASID_MASK <<
- KGSL_IOMMU_CONTEXTIDR_ASID_SHIFT));
-}
-
-/*
* kgsl_iommu_default_setstate - Change the IOMMU pagetable or flush IOMMU tlb
* of the primary context bank
* @mmu - Pointer to mmu structure
@@ -1066,15 +983,6 @@
temp = KGSL_IOMMU_GET_IOMMU_REG(
iommu->iommu_units[i].reg_map.hostptr,
KGSL_IOMMU_CONTEXT_USER, TTBR0);
- /* Set asid */
- KGSL_IOMMU_SET_IOMMU_REG(
- iommu->iommu_units[i].reg_map.hostptr,
- KGSL_IOMMU_CONTEXT_USER, CONTEXTIDR,
- kgsl_iommu_get_hwpagetable_asid(mmu));
- mb();
- temp = KGSL_IOMMU_GET_IOMMU_REG(
- iommu->iommu_units[i].reg_map.hostptr,
- KGSL_IOMMU_CONTEXT_USER, CONTEXTIDR);
}
}
/* Flush tlb */
@@ -1082,8 +990,8 @@
for (i = 0; i < iommu->unit_count; i++) {
KGSL_IOMMU_SET_IOMMU_REG(
iommu->iommu_units[i].reg_map.hostptr,
- KGSL_IOMMU_CONTEXT_USER, CTX_TLBIASID,
- kgsl_iommu_get_hwpagetable_asid(mmu));
+ KGSL_IOMMU_CONTEXT_USER, CTX_TLBIALL,
+ 1);
mb();
}
}
@@ -1139,7 +1047,6 @@
.mmu_get_current_ptbase = kgsl_iommu_get_current_ptbase,
.mmu_enable_clk = kgsl_iommu_enable_clk,
.mmu_disable_clk_on_ts = kgsl_iommu_disable_clk_on_ts,
- .mmu_get_hwpagetable_asid = kgsl_iommu_get_hwpagetable_asid,
.mmu_get_pt_lsb = kgsl_iommu_get_pt_lsb,
.mmu_get_reg_map_desc = kgsl_iommu_get_reg_map_desc,
};
diff --git a/drivers/gpu/msm/kgsl_iommu.h b/drivers/gpu/msm/kgsl_iommu.h
index 354a5cf..f14db93 100644
--- a/drivers/gpu/msm/kgsl_iommu.h
+++ b/drivers/gpu/msm/kgsl_iommu.h
@@ -23,15 +23,8 @@
#define KGSL_IOMMU_TTBR0_PA_MASK 0x0003FFFF
#define KGSL_IOMMU_TTBR0_PA_SHIFT 14
#define KGSL_IOMMU_CTX_TLBIALL 0x800
-#define KGSL_IOMMU_CONTEXTIDR 0x8
-#define KGSL_IOMMU_CONTEXTIDR_ASID_MASK 0xFF
-#define KGSL_IOMMU_CONTEXTIDR_ASID_SHIFT 0
-#define KGSL_IOMMU_CTX_TLBIASID 0x804
#define KGSL_IOMMU_CTX_SHIFT 12
-#define KGSL_IOMMU_MAX_ASIDS 256
-#define KGSL_IOMMU_ASID_REUSE 2
-
/*
* Max number of iommu units that the gpu core can have
* On APQ8064, KGSL can control a maximum of 2 IOMMU units.
@@ -106,10 +99,6 @@
* @clk_event_queued: Indicates whether an event to disable clocks
* is already queued or not
* @device: Pointer to kgsl device
- * @asids: A bit structure indicating which id's are presently used
- * @asid: Contains the initial value of IOMMU_CONTEXTIDR when a domain
- * is first attached
- * asid_reuse: Holds the number of times the reuse asid is reused
*/
struct kgsl_iommu {
struct kgsl_iommu_unit iommu_units[KGSL_IOMMU_MAX_UNITS];
@@ -117,21 +106,16 @@
unsigned int iommu_last_cmd_ts;
bool clk_event_queued;
struct kgsl_device *device;
- unsigned long *asids;
- unsigned int asid;
- unsigned int asid_reuse;
};
/*
* struct kgsl_iommu_pt - Iommu pagetable structure private to kgsl driver
* @domain: Pointer to the iommu domain that contains the iommu pagetable
* @iommu: Pointer to iommu structure
- * @asid: The asid assigned to this domain
*/
struct kgsl_iommu_pt {
struct iommu_domain *domain;
struct kgsl_iommu *iommu;
- unsigned int asid;
};
#endif
diff --git a/drivers/gpu/msm/kgsl_mmu.h b/drivers/gpu/msm/kgsl_mmu.h
index f8a2ea4..bc6ec8e 100644
--- a/drivers/gpu/msm/kgsl_mmu.h
+++ b/drivers/gpu/msm/kgsl_mmu.h
@@ -136,7 +136,6 @@
(struct kgsl_mmu *mmu, uint32_t ts, bool ts_valid);
int (*mmu_enable_clk)
(struct kgsl_mmu *mmu, int ctx_id);
- int (*mmu_get_hwpagetable_asid)(struct kgsl_mmu *mmu);
int (*mmu_get_pt_lsb)(struct kgsl_mmu *mmu,
unsigned int unit_id,
enum kgsl_iommu_context_id ctx_id);
@@ -278,14 +277,6 @@
return 0;
}
-static inline int kgsl_mmu_get_hwpagetable_asid(struct kgsl_mmu *mmu)
-{
- if (mmu->mmu_ops && mmu->mmu_ops->mmu_get_hwpagetable_asid)
- return mmu->mmu_ops->mmu_get_hwpagetable_asid(mmu);
- else
- return 0;
-}
-
static inline int kgsl_mmu_enable_clk(struct kgsl_mmu *mmu,
int ctx_id)
{