msm: kgsl: Remove the use of asid
Remove the use of asid(application space ID) from the kgsl driver
for IOMMU since it's known to cause to stability issues on the
2D core
Change-Id: I92f82ebb0941296c7ad625dd833822dd918fe386
CRs-fixed: 379439
Signed-off-by: Shubhraprakash Das <sadas@codeaurora.org>
diff --git a/drivers/gpu/msm/adreno.c b/drivers/gpu/msm/adreno.c
index 2f48999..fc51970 100644
--- a/drivers/gpu/msm/adreno.c
+++ b/drivers/gpu/msm/adreno.c
@@ -303,8 +303,8 @@
device->mmu.setstate_memory.gpuaddr +
KGSL_IOMMU_SETSTATE_NOP_OFFSET);
+ pt_val = kgsl_mmu_pt_get_base_addr(device->mmu.hwpagetable);
if (flags & KGSL_MMUFLAGS_PTUPDATE) {
- pt_val = kgsl_mmu_pt_get_base_addr(device->mmu.hwpagetable);
/*
* We need to perfrom the following operations for all
* IOMMU units
@@ -338,24 +338,6 @@
reg_pt_val,
device->mmu.setstate_memory.gpuaddr +
KGSL_IOMMU_SETSTATE_NOP_OFFSET);
-
- /* set the asid */
- *cmds++ = cp_type3_packet(CP_MEM_WRITE, 2);
- *cmds++ = reg_map_desc[i]->gpuaddr +
- (KGSL_IOMMU_CONTEXT_USER <<
- KGSL_IOMMU_CTX_SHIFT) + KGSL_IOMMU_CONTEXTIDR;
- *cmds++ = kgsl_mmu_get_hwpagetable_asid(&device->mmu);
- *cmds++ = cp_type3_packet(CP_WAIT_FOR_IDLE, 1);
- *cmds++ = 0x00000000;
-
- /* Read back asid to ensure above write completes */
- cmds += adreno_add_read_cmds(device, cmds,
- reg_map_desc[i]->gpuaddr +
- (KGSL_IOMMU_CONTEXT_USER <<
- KGSL_IOMMU_CTX_SHIFT) + KGSL_IOMMU_CONTEXTIDR,
- kgsl_mmu_get_hwpagetable_asid(&device->mmu),
- device->mmu.setstate_memory.gpuaddr +
- KGSL_IOMMU_SETSTATE_NOP_OFFSET);
}
/* invalidate all base pointers */
*cmds++ = cp_type3_packet(CP_INVALIDATE_STATE, 1);
@@ -367,15 +349,21 @@
}
if (flags & KGSL_MMUFLAGS_TLBFLUSH) {
/*
- * tlb flush based on asid, no need to flush entire tlb
+ * tlb flush
*/
for (i = 0; i < num_iommu_units; i++) {
+ reg_pt_val = (pt_val &
+ (KGSL_IOMMU_TTBR0_PA_MASK <<
+ KGSL_IOMMU_TTBR0_PA_SHIFT)) +
+ kgsl_mmu_get_pt_lsb(&device->mmu, i,
+ KGSL_IOMMU_CONTEXT_USER);
+
*cmds++ = cp_type3_packet(CP_MEM_WRITE, 2);
*cmds++ = (reg_map_desc[i]->gpuaddr +
(KGSL_IOMMU_CONTEXT_USER <<
KGSL_IOMMU_CTX_SHIFT) +
- KGSL_IOMMU_CTX_TLBIASID);
- *cmds++ = kgsl_mmu_get_hwpagetable_asid(&device->mmu);
+ KGSL_IOMMU_CTX_TLBIALL);
+ *cmds++ = 1;
cmds += __adreno_add_idle_indirect_cmds(cmds,
device->mmu.setstate_memory.gpuaddr +
@@ -384,9 +372,8 @@
cmds += adreno_add_read_cmds(device, cmds,
reg_map_desc[i]->gpuaddr +
(KGSL_IOMMU_CONTEXT_USER <<
- KGSL_IOMMU_CTX_SHIFT) +
- KGSL_IOMMU_CONTEXTIDR,
- kgsl_mmu_get_hwpagetable_asid(&device->mmu),
+ KGSL_IOMMU_CTX_SHIFT) + KGSL_IOMMU_TTBR0,
+ reg_pt_val,
device->mmu.setstate_memory.gpuaddr +
KGSL_IOMMU_SETSTATE_NOP_OFFSET);
}