)]}'
{
  "commit": "86efef50cfff9905c4e4ec64f3d3d3b299226674",
  "tree": "e60029ca0b888b1f01a049d9e512ef524b2279e3",
  "parents": [
    "fa5cecd111d235819a1d807d43216ae459a0dd6f"
  ],
  "author": {
    "name": "Stephane Eranian",
    "email": "eranian@hpl.hp.com",
    "time": "Thu Dec 07 02:14:02 2006 +0100"
  },
  "committer": {
    "name": "Andi Kleen",
    "email": "andi@basil.nowhere.org",
    "time": "Thu Dec 07 02:14:02 2006 +0100"
  },
  "message": "[PATCH] x86-64: x86-64 add Intel Core related PMU MSRs definitions\n\nAdd o the x86-64 tree a bunch of MSRs related to performance\nmonitoring for the processors based on Intel Core microarchitecture.\nIt also adds some architectural MSRs for PEBS. A similar patch for i386 will\nfollow.\n\nchangelog:\n\t- add Intel Precise-Event Based sampling (PEBS) related MSR\n\t- add Intel Data Save (DS) Area related MSR\n\t- add Intel Core microarchitecure performance counter MSRs\n\nSigned-off-by: stephane eranian \u003ceranian@hpl.hp.com\u003e\nSigned-off-by: Andi Kleen \u003cak@suse.de\u003e\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "37e194169fac2f2793894331eb9ec34d81401dfa",
      "old_mode": 33188,
      "old_path": "include/asm-x86_64/msr.h",
      "new_id": "a745c5008a6017e0fd9ad1b36a444fb33711d032",
      "new_mode": 33188,
      "new_path": "include/asm-x86_64/msr.h"
    }
  ]
}