)]}'
{
  "commit": "89b831ef8bf5cfbb357dbc0a2e07700d7f20eec5",
  "tree": "25118081599eab69bd20d1a1b34ba0f8f679f24f",
  "parents": [
    "979edfadbae2286eec5b46143c00e81bca96498e"
  ],
  "author": {
    "name": "Jacob Shin",
    "email": "jacob.shin@amd.com",
    "time": "Sat Nov 05 17:25:53 2005 +0100"
  },
  "committer": {
    "name": "Linus Torvalds",
    "email": "torvalds@g5.osdl.org",
    "time": "Mon Nov 14 19:55:13 2005 -0800"
  },
  "message": "[PATCH] x86_64: Support for AMD specific MCE Threshold.\n\nMC4_MISC - DRAM Errors Threshold Register realized under AMD K8 Rev F.\nThis register is used to count correctable and uncorrectable ECC errors that occur during DRAM read operations.\nThe user may interface through sysfs files in order to change the threshold configuration.\n\nbank%d/error_count - reads current error count, write to clear.\nbank%d/interrupt_enable - set/clear interrupt enable.\nbank%d/threshold_limit - read/write the threshold limit.\n\nAPIC vector 0xF9 in hw_irq.h.\n5 software defined bank ids in mce.h.\nnew apic.c function to setup threshold apic lvt.\ndefaults to interrupt off, count enabled, and threshold limit max.\nsysfs interface created on /sys/devices/system/threshold.\n\nAK: added some ifdefs to make it compile on UP\n\nSigned-off-by: Jacob Shin \u003cjacob.shin@amd.com\u003e\nSigned-off-by: Andi Kleen \u003cak@suse.de\u003e\nSigned-off-by: Linus Torvalds \u003ctorvalds@osdl.org\u003e\n",
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