| commit | 8b1c2ba274c8416afb7eab3bd788f98a917efe06 | [log] [tgz] |
|---|---|---|
| author | San Mehat <san@google.com> | Mon Nov 16 10:17:30 2009 -0800 |
| committer | Daniel Walker <dwalker@codeaurora.org> | Thu Mar 18 13:15:47 2010 -0700 |
| tree | aeee912e0f9fd054bd8bf4bf436426ba07ef2077 | |
| parent | 865c8064a2fb07100525097983966b8e789bde1a [diff] |
mmc: msm_sdcc: Wrap readl/writel calls with appropriate clk delays
As it turns out, all sdcc register writes must be delayed by at
least 3 core clock cycles for the writes to take effect. *sigh*
Also removes the 30us constant delay on clock enable in favor
of a 3 core clock delay.
Signed-off-by: San Mehat <san@google.com>
Signed-off-by: Daniel Walker <dwalker@codeaurora.org>