)]}'
{
  "commit": "8b1c2ba274c8416afb7eab3bd788f98a917efe06",
  "tree": "aeee912e0f9fd054bd8bf4bf436426ba07ef2077",
  "parents": [
    "865c8064a2fb07100525097983966b8e789bde1a"
  ],
  "author": {
    "name": "San Mehat",
    "email": "san@google.com",
    "time": "Mon Nov 16 10:17:30 2009 -0800"
  },
  "committer": {
    "name": "Daniel Walker",
    "email": "dwalker@codeaurora.org",
    "time": "Thu Mar 18 13:15:47 2010 -0700"
  },
  "message": "mmc: msm_sdcc: Wrap readl/writel calls with appropriate clk delays\n\nAs it turns out, all sdcc register writes must be delayed by at\nleast 3 core clock cycles for the writes to take effect. *sigh*\n\n    Also removes the 30us constant delay on clock enable in favor\nof a 3 core clock delay.\n\nSigned-off-by: San Mehat \u003csan@google.com\u003e\nSigned-off-by: Daniel Walker \u003cdwalker@codeaurora.org\u003e\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "b4b637223b7550c8ae5bc3e2c4d442bbfafe7395",
      "old_mode": 33188,
      "old_path": "drivers/mmc/host/msm_sdcc.c",
      "new_id": "3b096f64ec5297afa8d8596970088e64f02e922b",
      "new_mode": 33188,
      "new_path": "drivers/mmc/host/msm_sdcc.c"
    }
  ]
}