msm: clock-8974: Fix GPLL0 configuration issue for acpuclock
GPLL0 is always expected to be on when Linux is running. It is required
for all active BMIC/EBI and NoC clock rates. acpuclock also makes the
assumption that GPLL0_AUX is an always-on source that can be safely
switched to at any time. For current builds used in pre-silicon
simulation environments, however, this is not true because:
1) The bootchain and RPM, which would normally vote for GPLL0 to remain
enabled are not presently in use, leaving clock-8974 as the only
voter for the PLL.
2) The clock driver de-asserts its vote for GPLL0 when there are no clock
driver clients requiring it, resulting in it turning off.
3) The AUX output of GPLL0 is never enabled due a typo in reg_init()
The first point was already addressed in clock-8974.c be enabling GPLL0 as
part of reg_init().
The second point is addressed now, by removing the enable mask for GPLL0.
This is simpler and more efficient than requiring acpuclock to vote for
the PLL. It also avoid the side-effect of blocking XO-shutdown that such
a vote would have if power-collapse were to occur while the CPU is running
from the PLL0 source (which should be allowed).
The third point is also addressed now by correcting the "PLL_AUX_OUTPUT"
macro.
Change-Id: I5abeb6497261119fd1ae674f8b901d360261932f
Signed-off-by: Matt Wagantall <mattw@codeaurora.org>
diff --git a/arch/arm/mach-msm/clock-8974.c b/arch/arm/mach-msm/clock-8974.c
index 63c89f6..48f16b0 100644
--- a/arch/arm/mach-msm/clock-8974.c
+++ b/arch/arm/mach-msm/clock-8974.c
@@ -619,7 +619,6 @@
static struct pll_vote_clk gpll0_clk_src = {
.en_reg = (void __iomem *)APCS_GPLL_ENA_VOTE_REG,
- .en_mask = BIT(0),
.status_reg = (void __iomem *)GPLL0_STATUS_REG,
.status_mask = BIT(17),
.parent = &cxo_clk_src.c,
@@ -5049,7 +5048,7 @@
.main_output_mask = BIT(0),
};
-#define PLL_AUX_OUTPUT BIT(1)
+#define PLL_AUX_OUTPUT_BIT 1
static void __init reg_init(void)
{
@@ -5070,7 +5069,7 @@
/* Active GPLL0's aux output. This is needed by acpuclock. */
regval = readl_relaxed(GCC_REG_BASE(GPLL0_USER_CTL_REG));
- regval |= BIT(PLL_AUX_OUTPUT);
+ regval |= BIT(PLL_AUX_OUTPUT_BIT);
writel_relaxed(regval, GCC_REG_BASE(GPLL0_USER_CTL_REG));
/* Vote for GPLL0 to turn on. Needed by acpuclock. */