)]}'
{
  "commit": "8c781bf77a339748839bfd5eedfe2ad3e0e05c4a",
  "tree": "b36feb822eaecec5735dcc18244503d5bb88e15e",
  "parents": [
    "abcdceb9d0bf39da7c7ff8bcdff6eb4d9dfec56f"
  ],
  "author": {
    "name": "Albert Lee",
    "email": "albertcc@tw.ibm.com",
    "time": "Tue Jun 26 13:43:15 2007 +0800"
  },
  "committer": {
    "name": "Jeff Garzik",
    "email": "jeff@garzik.org",
    "time": "Mon Jul 02 10:12:34 2007 -0400"
  },
  "message": "libata: pata_pdc2027x PLL input clock fix\n\nRecently the PLL input clock of pata_pdc2027x is sometimes detected\nhiger than expected (e.g. 20.027 MHz compared to 16.714 MHz).\nIt seems sometimes the mdelay() function is not as precise as it\nused to be. Per Alan\u0027s advice, HT or power management might affect\nthe precision of mdelay().\n\nThis patch calls gettimeofday() to mesure the time elapsed and\ncalculate the PLL input clock accordingly.\n\nSigned-off-by: Albert Lee \u003calbertcc@tw.ibm.com\u003e\nCc: Alan Cox \u003calan@lxorguk.ukuu.org.uk\u003e\nSigned-off-by: Jeff Garzik \u003cjeff@garzik.org\u003e\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "0d2cc49fde4b6a884e7c73e047b4f05c12cdf642",
      "old_mode": 33188,
      "old_path": "drivers/ata/pata_pdc2027x.c",
      "new_id": "69a5aa4949f5b358bf6382eaceea694fb92a91c1",
      "new_mode": 33188,
      "new_path": "drivers/ata/pata_pdc2027x.c"
    }
  ]
}