[ARM] 2887/1: OMAP 2/4: Update files common to omap1 and omap2, take 2
Patch from Tony Lindgren
This patch syncs the mainline kernel with linux-omap tree.
The highlights of the patch are:
- Clock updates by Tuukka Tikkanen, Juha Yrjola,
Daniel Petrini and Tony Lindgren
- DMA fixes by Imre Deak, Juha Yrjola and Daniel Petrini
- Add support to dual-mode hardware timers by Lauri Leukkunen
- GPIO support for 24xx by Paul Mundt
- GPIO wake-up support by Tony Lindgren
- Better GPIO interrupt handler to not lose interrupts by
Ralph Walden and Ladislav Michl
- Power Management updates by Tuukka Tikkanen
- Make Power Management code use new SRAM functions by
Tony Lindgren
Signed-off-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
diff --git a/arch/arm/plat-omap/clock.c b/arch/arm/plat-omap/clock.c
index 59d91b3..52a58b2 100644
--- a/arch/arm/plat-omap/clock.c
+++ b/arch/arm/plat-omap/clock.c
@@ -21,6 +21,7 @@
#include <asm/arch/usb.h>
#include "clock.h"
+#include "sram.h"
static LIST_HEAD(clocks);
static DECLARE_MUTEX(clocks_sem);
@@ -141,7 +142,7 @@
static struct clk armper_ck = {
.name = "armper_ck",
.parent = &ck_dpll1,
- .flags = CLOCK_IN_OMAP730 | CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
+ .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
RATE_CKCTL,
.enable_reg = ARM_IDLECT2,
.enable_bit = EN_PERCK,
@@ -385,7 +386,8 @@
.name = "uart2_ck",
/* Direct from ULPD, no parent */
.rate = 12000000,
- .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | ENABLE_REG_32BIT,
+ .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | ENABLE_REG_32BIT |
+ ALWAYS_ENABLED,
.enable_reg = MOD_CONF_CTRL_0,
.enable_bit = 30, /* Chooses between 12MHz and 48MHz */
.set_rate = &set_uart_rate,
@@ -443,6 +445,15 @@
.enable_bit = 8 /* UHOST_EN */,
};
+static struct clk usb_dc_ck = {
+ .name = "usb_dc_ck",
+ /* Direct from ULPD, no parent */
+ .rate = 48000000,
+ .flags = CLOCK_IN_OMAP16XX | RATE_FIXED,
+ .enable_reg = SOFT_REQ_REG,
+ .enable_bit = 4,
+};
+
static struct clk mclk_1510 = {
.name = "mclk",
/* Direct from ULPD, no parent. May be enabled by ext hardware. */
@@ -552,6 +563,7 @@
&uart3_16xx,
&usb_clko,
&usb_hhc_ck1510, &usb_hhc_ck16xx,
+ &usb_dc_ck,
&mclk_1510, &mclk_16xx,
&bclk_1510, &bclk_16xx,
&mmc1_ck,
@@ -946,14 +958,13 @@
if (!ptr->rate)
return -EINVAL;
- if (!ptr->rate)
- return -EINVAL;
+ /*
+ * In most cases we should not need to reprogram DPLL.
+ * Reprogramming the DPLL is tricky, it must be done from SRAM.
+ */
+ omap_sram_reprogram_clock(ptr->dpllctl_val, ptr->ckctl_val);
- if (unlikely(ck_dpll1.rate == 0)) {
- omap_writew(ptr->dpllctl_val, DPLL_CTL);
- ck_dpll1.rate = ptr->pll_rate;
- }
- omap_writew(ptr->ckctl_val, ARM_CKCTL);
+ ck_dpll1.rate = ptr->pll_rate;
propagate_rate(&ck_dpll1);
return 0;
}
@@ -1224,9 +1235,11 @@
#endif
/* Cache rates for clocks connected to ck_ref (not dpll1) */
propagate_rate(&ck_ref);
- printk(KERN_INFO "Clocking rate (xtal/DPLL1/MPU): %ld.%01ld/%ld/%ld MHz\n",
+ printk(KERN_INFO "Clocking rate (xtal/DPLL1/MPU): "
+ "%ld.%01ld/%ld.%01ld/%ld.%01ld MHz\n",
ck_ref.rate / 1000000, (ck_ref.rate / 100000) % 10,
- ck_dpll1.rate, arm_ck.rate);
+ ck_dpll1.rate / 1000000, (ck_dpll1.rate / 100000) % 10,
+ arm_ck.rate / 1000000, (arm_ck.rate / 100000) % 10);
#ifdef CONFIG_MACH_OMAP_PERSEUS2
/* Select slicer output as OMAP input clock */
@@ -1271,7 +1284,9 @@
struct clk *p;
__u32 regval32;
- omap_writew(0, SOFT_REQ_REG);
+ /* USB_REQ_EN will be disabled later if necessary (usb_dc_ck) */
+ regval32 = omap_readw(SOFT_REQ_REG) & (1 << 4);
+ omap_writew(regval32, SOFT_REQ_REG);
omap_writew(0, SOFT_REQ_REG2);
list_for_each_entry(p, &clocks, node) {