)]}'
{
  "commit": "9448b8f6a014f46450ef65d81c0be2ca5a81c867",
  "tree": "fc1b5ece555ed23b3918151df58608ac0abbc05c",
  "parents": [
    "f0ec69e52989986e861a352099803cbb77ca53ba"
  ],
  "author": {
    "name": "Manish Lachwani",
    "email": "mlachwani@mvista.com",
    "time": "Thu Oct 05 16:30:44 2006 -0700"
  },
  "committer": {
    "name": "Ralf Baechle",
    "email": "ralf@linux-mips.org",
    "time": "Mon Oct 30 21:41:28 2006 +0000"
  },
  "message": "[MIPS] Make SB1 cache flushes not to use on_each_cpu\n\nThis fixes the\n\n  start_kernel(): bug: interrupts were enabled early\n\nmessages.\n\nSigned-off-by: Manish Lachwani \u003cmlachwani@mvista.com\u003e\nSigned-off-by: Ralf Baechle \u003cralf@linux-mips.org\u003e\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "f2941b4c9f33b90b34a3fe83137b90a1c238df1c",
      "old_mode": 33188,
      "old_path": "arch/mips/mm/c-sb1.c",
      "new_id": "ea49a775bf2859f0afc1fbfda7d2bab626c3f1c6",
      "new_mode": 33188,
      "new_path": "arch/mips/mm/c-sb1.c"
    }
  ]
}