msm: clock-copper: Switch max_div values from 16 to 15.

The dividers on branches (cdivs) can be configured using
4 bits in the CBCR register. The range of possible values
is therefore 0 through 15. Fix max_div to reflect this
maximum value.

Change-Id: I11325eb371d93254b5327b1ded56b1820661713f
Signed-off-by: Vikram Mulukutla <markivx@codeaurora.org>
diff --git a/arch/arm/mach-msm/clock-copper.c b/arch/arm/mach-msm/clock-copper.c
index e96aa3f..99443a5 100644
--- a/arch/arm/mach-msm/clock-copper.c
+++ b/arch/arm/mach-msm/clock-copper.c
@@ -4011,7 +4011,7 @@
 	.cbcr_reg = AUDIO_CORE_LPAIF_CODEC_SPKR_IBIT_CBCR,
 	.parent = &audio_core_lpaif_codec_spkr_clk_src.c,
 	.has_sibling = 1,
-	.max_div = 16,
+	.max_div = 15,
 	.base = &virt_bases[LPASS_BASE],
 	.c = {
 		.dbg_name = "audio_core_lpaif_codec_spkr_clk_src",
@@ -4047,7 +4047,7 @@
 	.cbcr_reg = AUDIO_CORE_LPAIF_PRI_IBIT_CBCR,
 	.parent = &audio_core_lpaif_pri_clk_src.c,
 	.has_sibling = 1,
-	.max_div = 16,
+	.max_div = 15,
 	.base = &virt_bases[LPASS_BASE],
 	.c = {
 		.dbg_name = "audio_core_lpaif_pri_ibit_clk",
@@ -4083,7 +4083,7 @@
 	.cbcr_reg = AUDIO_CORE_LPAIF_SEC_IBIT_CBCR,
 	.parent = &audio_core_lpaif_sec_clk_src.c,
 	.has_sibling = 1,
-	.max_div = 16,
+	.max_div = 15,
 	.base = &virt_bases[LPASS_BASE],
 	.c = {
 		.dbg_name = "audio_core_lpaif_sec_ibit_clk",
@@ -4119,7 +4119,7 @@
 	.cbcr_reg = AUDIO_CORE_LPAIF_TER_IBIT_CBCR,
 	.parent = &audio_core_lpaif_ter_clk_src.c,
 	.has_sibling = 1,
-	.max_div = 16,
+	.max_div = 15,
 	.base = &virt_bases[LPASS_BASE],
 	.c = {
 		.dbg_name = "audio_core_lpaif_ter_ibit_clk",
@@ -4155,7 +4155,7 @@
 	.cbcr_reg = AUDIO_CORE_LPAIF_QUAD_IBIT_CBCR,
 	.parent = &audio_core_lpaif_quad_clk_src.c,
 	.has_sibling = 1,
-	.max_div = 16,
+	.max_div = 15,
 	.base = &virt_bases[LPASS_BASE],
 	.c = {
 		.dbg_name = "audio_core_lpaif_quad_ibit_clk",