EHCI: HSIC: improve port resume handling
This patch does the following to ensure that port is resumed
properly and SOF are sent with in 3 msec after the port resume
completion.
1. Use relaxed variants of readl and writel functions to access
registers in the resume critical path to avoid any delays introduced
by barriers.
2. Use ktime based checks to see if controller is started with in 3
msec after port resume is completed. These checks will catch the
cases where there is some delay between port resume and GPT timers
programming.
3. There is no good in polling for PORT_RESUME bit to be cleared.
Controller clears it after ~21 msec. Give 22 msec delay after port
resume and start the controller. Also add a ktime basec check to see
if controller is started with in 3 msec after port resume is completed.
If this timing is not met, perform the tight loop sequence again at
most 3 times.
CRs-Fixed: 553845
Change-Id: I29eab2fa0f684d91e1ac52d14faaffde1113b79b
Signed-off-by: Pavankumar Kondeti <pkondeti@codeaurora.org>
diff --git a/drivers/usb/host/ehci-msm-hsic.c b/drivers/usb/host/ehci-msm-hsic.c
index 7aaacd3..3688885 100644
--- a/drivers/usb/host/ehci-msm-hsic.c
+++ b/drivers/usb/host/ehci-msm-hsic.c
@@ -39,6 +39,7 @@
#include <linux/wait.h>
#include <linux/pm_qos.h>
#include <linux/irq.h>
+#include <linux/ktime.h>
#include <mach/msm_bus.h>
#include <mach/clk.h>
@@ -52,6 +53,10 @@
#define USB_REG_START_OFFSET 0x90
#define USB_REG_END_OFFSET 0x250
+#define RESUME_RETRY_LIMIT 3
+#define RESUME_SIGNAL_TIME_USEC (21 * 1000)
+#define RESUME_SIGNAL_TIME_SOF_USEC (23 * 1000)
+
static struct workqueue_struct *ehci_wq;
struct ehci_timer {
#define GPT_LD(p) ((p) & 0x00FFFFFF)
@@ -99,6 +104,7 @@
int resume_again;
int bus_reset;
int reset_again;
+ ktime_t resume_start_t;
struct pm_qos_request pm_qos_req_dma;
};
@@ -877,6 +883,15 @@
timeleft = GPT_CNT(ehci_readl(ehci,
&mehci->timer->gptimer1_ctrl));
+ if (!mehci->bus_reset) {
+ if (ktime_us_delta(ktime_get(), mehci->resume_start_t) >
+ RESUME_SIGNAL_TIME_SOF_USEC) {
+ dbg_log_event(NULL, "FPR: GPT prog invalid",
+ timeleft);
+ pr_err("HSIC GPT timer prog invalid\n");
+ timeleft = 0;
+ }
+ }
if (timeleft) {
if (mehci->bus_reset) {
ret = msm_hsic_reset_done(hcd);
@@ -885,9 +900,18 @@
dbg_log_event(NULL, "RESET: fail", 0);
}
} else {
- ehci_writel(ehci, ehci_readl(ehci,
+ writel_relaxed(readl_relaxed(
&ehci->regs->command) | CMD_RUN,
&ehci->regs->command);
+ if (ktime_us_delta(ktime_get(),
+ mehci->resume_start_t) >
+ RESUME_SIGNAL_TIME_SOF_USEC) {
+ dbg_log_event(NULL,
+ "FPR: resume prog invalid",
+ timeleft);
+ pr_err("HSIC resume fail. retrying\n");
+ mehci->resume_again = 1;
+ }
}
} else {
if (mehci->bus_reset)
@@ -1056,9 +1080,6 @@
return ehci_bus_suspend(hcd);
}
-#define RESUME_RETRY_LIMIT 3
-#define RESUME_SIGNAL_TIME_USEC (21 * 1000)
-#define RESUME_SIGNAL_TIME_SOF_USEC (23 * 1000)
static int msm_hsic_resume_thread(void *data)
{
struct msm_hsic_hcd *mehci = data;
@@ -1068,6 +1089,7 @@
unsigned long resume_needed = 0;
int retry_cnt = 0;
int tight_resume = 0;
+ int tight_count = 0;
struct msm_hsic_host_platform_data *pdata = mehci->dev->platform_data;
s32 next_latency = 0;
@@ -1099,19 +1121,19 @@
/* at least some APM implementations will try to deliver
* IRQs right away, so delay them until we're ready.
*/
- ehci_writel(ehci, 0, &ehci->regs->intr_enable);
+ writel_relaxed(0, &ehci->regs->intr_enable);
/* re-init operational registers */
- ehci_writel(ehci, 0, &ehci->regs->segment);
- ehci_writel(ehci, ehci->periodic_dma, &ehci->regs->frame_list);
- ehci_writel(ehci, (u32) ehci->async->qh_dma, &ehci->regs->async_next);
+ writel_relaxed(0, &ehci->regs->segment);
+ writel_relaxed(ehci->periodic_dma, &ehci->regs->frame_list);
+ writel_relaxed((u32) ehci->async->qh_dma, &ehci->regs->async_next);
/*CMD_RUN will be set after, PORT_RESUME gets cleared*/
if (ehci->resume_sof_bug)
ehci->command &= ~CMD_RUN;
/* restore CMD_RUN, framelist size, and irq threshold */
- ehci_writel(ehci, ehci->command, &ehci->regs->command);
+ writel_relaxed(ehci->command, &ehci->regs->command);
/* manually resume the ports we suspended during bus_suspend() */
resume_again:
@@ -1121,15 +1143,15 @@
tight_resume = 1;
}
-
- temp = ehci_readl(ehci, &ehci->regs->port_status[0]);
+ temp = readl_relaxed(&ehci->regs->port_status[0]);
temp &= ~(PORT_RWC_BITS | PORT_WAKE_BITS);
if (test_bit(0, &ehci->bus_suspended) && (temp & PORT_SUSPEND)) {
temp |= PORT_RESUME;
set_bit(0, &resume_needed);
}
+ mehci->resume_start_t = ktime_get();
dbg_log_event(NULL, "FPR: Set", temp);
- ehci_writel(ehci, temp, &ehci->regs->port_status[0]);
+ writel_relaxed(temp, &ehci->regs->port_status[0]);
/* HSIC controller has a h/w bug due to which it can try to send SOFs
* (start of frames) during port resume resulting in phy lockup. HSIC hw
@@ -1144,30 +1166,41 @@
if (ehci->resume_sof_bug && resume_needed) {
if (!tight_resume) {
mehci->resume_again = 0;
- ehci_writel(ehci, GPT_LD(RESUME_SIGNAL_TIME_USEC - 1),
+ writel_relaxed(GPT_LD(RESUME_SIGNAL_TIME_USEC - 1),
&mehci->timer->gptimer0_ld);
- ehci_writel(ehci, GPT_RESET | GPT_RUN,
+ writel_relaxed(GPT_RESET | GPT_RUN,
&mehci->timer->gptimer0_ctrl);
- ehci_writel(ehci, INTR_MASK | STS_GPTIMER0_INTERRUPT,
+ writel_relaxed(INTR_MASK | STS_GPTIMER0_INTERRUPT,
&ehci->regs->intr_enable);
- ehci_writel(ehci, GPT_LD(
- RESUME_SIGNAL_TIME_SOF_USEC - 1),
+ writel_relaxed(GPT_LD(RESUME_SIGNAL_TIME_SOF_USEC - 1),
&mehci->timer->gptimer1_ld);
- ehci_writel(ehci, GPT_RESET | GPT_RUN,
+ writel_relaxed(GPT_RESET | GPT_RUN,
&mehci->timer->gptimer1_ctrl);
+ dbg_log_event(NULL, "GPT timer prog done", 0);
spin_unlock_irq(&ehci->lock);
wait_for_completion(&mehci->gpt0_completion);
spin_lock_irq(&ehci->lock);
} else {
- dbg_log_event(NULL, "FPR: Tightloop", 0);
+ dbg_log_event(NULL, "FPR: Tightloop", tight_count);
/* do the resume in a tight loop */
- handshake(ehci, &ehci->regs->port_status[0],
- PORT_RESUME, 0, 22 * 1000);
- ehci_writel(ehci, ehci_readl(ehci,
- &ehci->regs->command) | CMD_RUN,
- &ehci->regs->command);
+ mdelay(22);
+ writel_relaxed(readl_relaxed(&ehci->regs->command) |
+ CMD_RUN, &ehci->regs->command);
+ if (ktime_us_delta(ktime_get(), mehci->resume_start_t) >
+ RESUME_SIGNAL_TIME_SOF_USEC) {
+ dbg_log_event(NULL, "FPR: Tightloop fail", 0);
+ if (++tight_count > 3) {
+ pr_err("HSIC resume failed\n");
+ mehci->resume_status = -ENODEV;
+ goto exit;
+ }
+ pr_err("FPR tight loop fail %d\n", tight_count);
+ mehci->resume_again = 1;
+ } else {
+ dbg_log_event(NULL, "FPR: Tightloop done", 0);
+ }
}
if (mehci->resume_again) {
@@ -1176,10 +1209,16 @@
dbg_log_event(NULL, "FPR: Re-Resume", retry_cnt);
pr_info("FPR: retry count: %d\n", retry_cnt);
spin_unlock_irq(&ehci->lock);
- temp = ehci_readl(ehci, &ehci->regs->port_status[0]);
+ temp = readl_relaxed(&ehci->regs->command);
+ if (temp & CMD_RUN) {
+ temp &= ~CMD_RUN;
+ writel_relaxed(temp, &ehci->regs->command);
+ dbg_log_event(NULL, "FPR: R/S cleared", 0);
+ }
+ temp = readl_relaxed(&ehci->regs->port_status[0]);
temp &= ~PORT_RWC_BITS;
temp |= PORT_SUSPEND;
- ehci_writel(ehci, temp, &ehci->regs->port_status[0]);
+ writel_relaxed(temp, &ehci->regs->port_status[0]);
/* Keep the bus idle for 5ms so that peripheral
* can detect and initiate suspend
*/
@@ -1194,6 +1233,7 @@
}
}
+ ehci->command |= CMD_RUN;
dbg_log_event(NULL, "FPR: RT-Done", 0);
mehci->resume_status = 1;
exit: