)]}'
{
  "commit": "98c5584cfc47932c4f3ccf5eee2e0bae1447b85e",
  "tree": "c067ac8bfc081bbe0b3073374cb15708458e04ab",
  "parents": [
    "09f94287f7260e03bbeab497e743691fafcc22c3"
  ],
  "author": {
    "name": "David S. Miller",
    "email": "davem@davemloft.net",
    "time": "Tue Jan 31 18:31:20 2006 -0800"
  },
  "committer": {
    "name": "David S. Miller",
    "email": "davem@sunset.davemloft.net",
    "time": "Mon Mar 20 01:11:17 2006 -0800"
  },
  "message": "[SPARC64]: Add infrastructure for dynamic TSB sizing.\n\nThis also cleans up tsb_context_switch().  The assembler\nroutine is now __tsb_context_switch() and the former is\nan inline function that picks out the bits from the mm_struct\nand passes it into the assembler code as arguments.\n\nsetup_tsb_parms() computes the locked TLB entry to map the\nTSB.  Later when we support using the physical address quad\nload instructions of Cheetah+ and later, we\u0027ll simply use\nthe physical address for the TSB register value and set\nthe map virtual and PTE both to zero.\n\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\n",
  "tree_diff": [
    {
      "type": "modify",
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      "old_mode": 33188,
      "old_path": "arch/sparc64/kernel/binfmt_aout32.c",
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      "new_mode": 33188,
      "new_path": "arch/sparc64/kernel/binfmt_aout32.c"
    },
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      "old_path": "arch/sparc64/kernel/process.c",
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      "new_path": "arch/sparc64/kernel/process.c"
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      "new_path": "arch/sparc64/kernel/tsb.S"
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      "new_path": "arch/sparc64/mm/tsb.c"
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      "new_path": "include/asm-sparc64/mmu.h"
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      "new_path": "include/asm-sparc64/mmu_context.h"
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}