msm: dcvs: enable/disable power collapse on CPU 0 only

Idle power collapse is not currently used on secondary cores
with DCVS, so it should not be manipulated after boot by DCVS.

(cherry picked from commit 7419749fb656f2f6b406d61c1df5993b2385af0a)

Change-Id: Id75829172c7c529d2b3e42a1ad406e591a94d1e9
Signed-off-by: Steve Muckle <smuckle@codeaurora.org>
diff --git a/arch/arm/mach-msm/msm_dcvs.c b/arch/arm/mach-msm/msm_dcvs.c
index ad1f669..9e0be63 100644
--- a/arch/arm/mach-msm/msm_dcvs.c
+++ b/arch/arm/mach-msm/msm_dcvs.c
@@ -370,9 +370,12 @@
 	core->freq_change_us = (uint32_t)ktime_to_us(
 					ktime_sub(ktime_get(), time_start));
 
-	mutex_lock(&param_update_mutex);
-	check_power_collapse_modes(core);
-	mutex_unlock(&param_update_mutex);
+	if (core->type == MSM_DCVS_CORE_TYPE_CPU &&
+	    core->type_core_num == 0) {
+		mutex_lock(&param_update_mutex);
+		check_power_collapse_modes(core);
+		mutex_unlock(&param_update_mutex);
+	}
 
 	/**
 	 * Update algorithm with new freq and time taken to change
@@ -581,7 +584,8 @@
 				mutex_unlock(&param_update_mutex);
 				return ret;
 			}
-			check_power_collapse_modes(core);
+			if (cpu == 0)
+				check_power_collapse_modes(core);
 		}
 		memcpy(&curr_params, new_params,
 		       sizeof(struct msm_dcvs_algo_param));