msm: clock: Respect voltage constraints for 9615 and 8960 UART dividers
The 16-bit fractional dividers used for these clocks should have
a clock rate no greater than 300MHz applied to their inputs when
running in low voltage mode. Increase the pre-dividers for rates
that previously violated this rule.
Change-Id: Ia7177c8643f8c8051ec9cef6cedcb2a7051d936c
Signed-off-by: Matt Wagantall <mattw@codeaurora.org>
diff --git a/arch/arm/mach-msm/clock-8960.c b/arch/arm/mach-msm/clock-8960.c
index afd3612d..e16cac5 100644
--- a/arch/arm/mach-msm/clock-8960.c
+++ b/arch/arm/mach-msm/clock-8960.c
@@ -1293,10 +1293,10 @@
}
static struct clk_freq_tbl clk_tbl_gsbi_uart[] = {
F_GSBI_UART( 0, gnd, 1, 0, 0),
- F_GSBI_UART( 1843200, pll8, 1, 3, 625),
- F_GSBI_UART( 3686400, pll8, 1, 6, 625),
- F_GSBI_UART( 7372800, pll8, 1, 12, 625),
- F_GSBI_UART(14745600, pll8, 1, 24, 625),
+ F_GSBI_UART( 1843200, pll8, 2, 6, 625),
+ F_GSBI_UART( 3686400, pll8, 2, 12, 625),
+ F_GSBI_UART( 7372800, pll8, 2, 24, 625),
+ F_GSBI_UART(14745600, pll8, 2, 48, 625),
F_GSBI_UART(16000000, pll8, 4, 1, 6),
F_GSBI_UART(24000000, pll8, 4, 1, 4),
F_GSBI_UART(32000000, pll8, 4, 1, 3),