msm: acpuclock-7201: Add acpu freq. tables for PLL1 at 737/589 MHz

PLL1 output frequency is now changed to 737.28MHz and 589.824MHz
for GSM and CDMA configuration resp. to achieve the 33% duty
cycle for adsp.

Add the required acpu frequency tables to reflect the same.

Tables for 245/196 PLL1 freq. are still kept to keep the backward
compatibility.

CRs-Fixed: 319835
Change-Id: Icae4c444efd693e87a26bf834727c04b30e1da88
Signed-off-by: Trilok Soni <tsoni@codeaurora.org>
diff --git a/arch/arm/mach-msm/acpuclock-7201.c b/arch/arm/mach-msm/acpuclock-7201.c
index 4702e51..0338d53 100644
--- a/arch/arm/mach-msm/acpuclock-7201.c
+++ b/arch/arm/mach-msm/acpuclock-7201.c
@@ -341,10 +341,86 @@
 	{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, {0, 0, 0, 0}, {0, 0, 0, 0} }
 };
 
+/* 7x27a pll2 at 1200mhz with GSM capable modem */
+static struct clkctl_acpu_speed pll0_960_pll1_737_pll2_1200_pll4_800[] = {
+	{ 0, 19200, ACPU_PLL_TCXO, 0, 0, 2400, 3, 0, 30720 },
+	{ 0, 61440, ACPU_PLL_1, 1, 11,  7680, 3, 1,  61440 },
+	{ 1, 122880, ACPU_PLL_1, 1, 5,  15360, 3, 2,  61440 },
+	{ 1, 245760, ACPU_PLL_1, 1, 2, 30720, 3, 3,  61440 },
+	{ 0, 300000, ACPU_PLL_2, 2, 3, 37500, 3, 4, 150000 },
+	{ 1, 320000, ACPU_PLL_0, 4, 2, 40000, 3, 4, 122880 },
+	{ 0, 400000, ACPU_PLL_4, 6, 1, 50000, 3, 4, 122880 },
+	{ 1, 480000, ACPU_PLL_0, 4, 1, 60000, 3, 5, 122880 },
+	{ 1, 600000, ACPU_PLL_2, 2, 1, 75000, 3, 6, 200000 },
+	{ 1, 800000, ACPU_PLL_4, 6, 0, 100000, 3, 7, 200000 },
+	{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, {0, 0, 0, 0}, {0, 0, 0, 0} }
+};
+
+/* 7x27a pll2 at 1200mhz with CDMA only modem */
+static struct clkctl_acpu_speed pll0_960_pll1_589_pll2_1200_pll4_800[] = {
+	{ 0, 19200, ACPU_PLL_TCXO, 0, 0, 2400, 3, 0, 24576 },
+	{ 0, 65536, ACPU_PLL_1, 1, 8,  8192, 3, 1,  49152 },
+	{ 1, 98304, ACPU_PLL_1, 1, 5,  12288, 3, 2,  49152 },
+	{ 1, 196608, ACPU_PLL_1, 1, 2, 24576, 3, 3,  98304 },
+	{ 0, 300000, ACPU_PLL_2, 2, 3, 37500, 3, 4, 120000 },
+	{ 1, 320000, ACPU_PLL_0, 4, 2, 40000, 3, 4, 120000 },
+	{ 0, 400000, ACPU_PLL_4, 6, 1, 50000, 3, 4, 120000 },
+	{ 1, 480000, ACPU_PLL_0, 4, 1, 60000, 3, 5, 120000 },
+	{ 1, 600000, ACPU_PLL_2, 2, 1, 75000, 3, 6, 200000 },
+	{ 1, 800000, ACPU_PLL_4, 6, 0, 100000, 3, 7, 200000 },
+	{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, {0, 0, 0, 0}, {0, 0, 0, 0} }
+};
+
+/* 7x27aa pll4 at 1008mhz with GSM capable modem */
+static struct clkctl_acpu_speed pll0_960_pll1_737_pll2_1200_pll4_1008[] = {
+	{ 0, 19200, ACPU_PLL_TCXO, 0, 0, 2400, 3, 0, 30720 },
+	{ 0, 61440, ACPU_PLL_1, 1, 11,  7680, 3, 1, 61440 },
+	{ 1, 122880, ACPU_PLL_1, 1, 5,  15360, 3, 2, 61440 },
+	{ 1, 245760, ACPU_PLL_1, 1, 2, 30720, 3, 3, 61440 },
+	{ 0, 300000, ACPU_PLL_2, 2, 3, 37500, 3, 4, 150000 },
+	{ 1, 320000, ACPU_PLL_0, 4, 2, 40000, 3, 4, 122880 },
+	{ 1, 480000, ACPU_PLL_0, 4, 1, 60000, 3, 5, 122880 },
+	{ 0, 504000, ACPU_PLL_4, 6, 1, 63000, 3, 6, 200000 },
+	{ 1, 600000, ACPU_PLL_2, 2, 1, 75000, 3, 6, 200000 },
+	{ 1, 1008000, ACPU_PLL_4, 6, 0, 126000, 3, 7, 200000},
+	{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, {0, 0, 0, 0}, {0, 0, 0, 0} }
+};
+
+/* 7x27aa pll4 at 1008mhz with CDMA capable modem */
+static struct clkctl_acpu_speed pll0_960_pll1_589_pll2_1200_pll4_1008[] = {
+	{ 0, 19200, ACPU_PLL_TCXO, 0, 0, 2400, 3, 0, 24576 },
+	{ 0, 65536, ACPU_PLL_1, 1, 8,  8192, 3, 1, 49152 },
+	{ 1, 98304, ACPU_PLL_1, 1, 5,  12288, 3, 2, 49152 },
+	{ 1, 196608, ACPU_PLL_1, 1, 2, 24576, 3, 3, 98304 },
+	{ 0, 300000, ACPU_PLL_2, 2, 3, 37500, 3, 4, 150000 },
+	{ 1, 320000, ACPU_PLL_0, 4, 2, 40000, 3, 4, 122880 },
+	{ 1, 480000, ACPU_PLL_0, 4, 1, 60000, 3, 5, 122880 },
+	{ 0, 504000, ACPU_PLL_4, 6, 1, 63000, 3, 6, 200000 },
+	{ 1, 600000, ACPU_PLL_2, 2, 1, 75000, 3, 6, 200000 },
+	{ 1, 1008000, ACPU_PLL_4, 6, 0, 126000, 3, 7, 200000},
+	{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, {0, 0, 0, 0}, {0, 0, 0, 0} }
+};
+
+/* 7x25a pll2 at 1200mhz with GSM capable modem */
+static struct clkctl_acpu_speed pll0_960_pll1_737_pll2_1200_pll4_800_25a[] = {
+	{ 0, 19200, ACPU_PLL_TCXO, 0, 0, 2400, 3, 0, 30720 },
+	{ 0, 61440, ACPU_PLL_1, 1, 11,  7680, 3, 1,  61440 },
+	{ 1, 122880, ACPU_PLL_1, 1, 5,  15360, 3, 2,  61440 },
+	{ 1, 245760, ACPU_PLL_1, 1, 2, 30720, 3, 3,  61440 },
+	{ 0, 300000, ACPU_PLL_2, 2, 3, 37500, 3, 4, 150000 },
+	{ 1, 320000, ACPU_PLL_0, 4, 2, 40000, 3, 4, 122880 },
+	{ 0, 400000, ACPU_PLL_4, 6, 1, 50000, 3, 4, 122880 },
+	{ 1, 480000, ACPU_PLL_0, 4, 1, 60000, 3, 5, 122880 },
+	{ 1, 600000, ACPU_PLL_2, 2, 1, 75000, 3, 6, 200000 },
+	{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, {0, 0, 0, 0}, {0, 0, 0, 0} }
+};
+
 #define PLL_0_MHZ	0
 #define PLL_196_MHZ	10
 #define PLL_245_MHZ	12
 #define PLL_491_MHZ	25
+#define PLL_589_MHZ	30
+#define PLL_737_MHZ	38
 #define PLL_768_MHZ	40
 #define PLL_800_MHZ	41
 #define PLL_960_MHZ	50
@@ -380,6 +456,10 @@
 	PLL_CONFIG(960, 196, 1200, 800),
 	PLL_CONFIG(960, 245, 1200, 1008),
 	PLL_CONFIG(960, 196, 1200, 1008),
+	PLL_CONFIG(960, 737, 1200, 800),
+	PLL_CONFIG(960, 589, 1200, 800),
+	PLL_CONFIG(960, 737, 1200, 1008),
+	PLL_CONFIG(960, 589, 1200, 1008),
 	{ 0, 0, 0, 0, 0 }
 };
 
@@ -868,6 +948,9 @@
 		if (pll1_l == PLL_245_MHZ) {
 			acpu_freq_tbl =
 				pll0_960_pll1_245_pll2_1200_pll4_800_25a;
+		} else if (pll1_l == PLL_737_MHZ) {
+			acpu_freq_tbl =
+				pll0_960_pll1_737_pll2_1200_pll4_800_25a;
 		}
 	} else {
 		/* Select the right table to use. */