)]}'
{
  "commit": "9bcb27217344c2c1389db3983a436e19484c2f50",
  "tree": "14c28cade53f8f64755f3d660149c3c7d501fd1d",
  "parents": [
    "0753f6e0a3d9568fb6b8e34753b944d9f8eed05b"
  ],
  "author": {
    "name": "Zhao Yakui",
    "email": "yakui.zhao@intel.com",
    "time": "Thu Nov 15 17:05:05 2007 +0800"
  },
  "committer": {
    "name": "Len Brown",
    "email": "len.brown@intel.com",
    "time": "Fri Nov 16 21:43:21 2007 -0500"
  },
  "message": "ACPI: Use _TSS for throttling control, when present. Add error checks.\n\n_TSS was erroneously ignored, in favor of the FADT.\n\nWhen TSS is used, the access width is included in the PTC control/status\nregister.  So it is unnecessary that the access bit width is multiplied by 8.\nAt the same time the bit_offset should be considered for system I/O Access.\n\nIt should be checked the bit_width and bit_offset of PTC regsiter in order to\navoid the failure of system I/O access. It means that bit_width plus\nbit_offset can\u0027t be greater than 32.\n\nSigned-off-by: Zhao Yakui \u003cyakui.zhao@intel.com\u003e\nSigned-off-by: Li Shaohua \u003cshaohua.li@intel.com\u003e\nSigned-off-by: Len Brown \u003clen.brown@intel.com\u003e\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "5c96ef18e94cbb126e8b2bab3c47ff8a1ade5b85",
      "old_mode": 33188,
      "old_path": "drivers/acpi/processor_throttling.c",
      "new_id": "f4b5f7d5dbe631ce57cbaa582afd79fd5ae5d107",
      "new_mode": 33188,
      "new_path": "drivers/acpi/processor_throttling.c"
    }
  ]
}