msm_fb: display: Enable H/W vsync in msm7x27a
Enable tearing effect control in msm7x27a using gpio.
CRs-Fixed: 289024
Signed-off-by: Jeevan Shriram <jshriram@codeaurora.org>
diff --git a/drivers/video/msm/mipi_dsi.c b/drivers/video/msm/mipi_dsi.c
index 61bb345..c3927c4 100644
--- a/drivers/video/msm/mipi_dsi.c
+++ b/drivers/video/msm/mipi_dsi.c
@@ -37,6 +37,8 @@
u32 dsi_irq;
+static boolean tlmm_settings = FALSE;
+
static int mipi_dsi_probe(struct platform_device *pdev);
static int mipi_dsi_remove(struct platform_device *pdev);
@@ -98,9 +100,10 @@
if (mfd->panel_info.type == MIPI_CMD_PANEL) {
if (pinfo->lcd.vsync_enable) {
- if (pinfo->lcd.hw_vsync_mode && vsync_gpio > 0)
- gpio_free(vsync_gpio);
-
+ if (pinfo->lcd.hw_vsync_mode && vsync_gpio > 0) {
+ if (MDP_REV_303 != mdp_rev)
+ gpio_free(vsync_gpio);
+ }
mipi_dsi_set_tear_off(mfd);
}
}
@@ -250,11 +253,45 @@
if (mfd->panel_info.type == MIPI_CMD_PANEL) {
if (pinfo->lcd.vsync_enable) {
if (pinfo->lcd.hw_vsync_mode && vsync_gpio > 0) {
- if (gpio_request(vsync_gpio, "MDP_VSYNC") == 0)
- gpio_direction_input(vsync_gpio);
- else
- pr_err("%s: unable to request gpio=%d\n",
- __func__, vsync_gpio);
+ if (mdp_rev >= MDP_REV_41) {
+ if (gpio_request(vsync_gpio,
+ "MDP_VSYNC") == 0)
+ gpio_direction_input(
+ vsync_gpio);
+ else
+ pr_err("%s: unable to \
+ request gpio=%d\n",
+ __func__, vsync_gpio);
+ } else if (mdp_rev == MDP_REV_303) {
+ if (!tlmm_settings && gpio_request(
+ vsync_gpio, "MDP_VSYNC") == 0) {
+ ret = gpio_tlmm_config(
+ GPIO_CFG(
+ vsync_gpio, 1,
+ GPIO_CFG_INPUT,
+ GPIO_CFG_PULL_DOWN,
+ GPIO_CFG_2MA),
+ GPIO_CFG_ENABLE);
+
+ if (ret) {
+ pr_err(
+ "%s: unable to config \
+ tlmm = %d\n",
+ __func__, vsync_gpio);
+ }
+ tlmm_settings = TRUE;
+
+ gpio_direction_input(
+ vsync_gpio);
+ } else {
+ if (!tlmm_settings) {
+ pr_err(
+ "%s: unable to request \
+ gpio=%d\n",
+ __func__, vsync_gpio);
+ }
+ }
+ }
}
mipi_dsi_set_tear_on(mfd);
}
diff --git a/drivers/video/msm/mipi_renesas.c b/drivers/video/msm/mipi_renesas.c
index 652ca29..77037b5 100644
--- a/drivers/video/msm/mipi_renesas.c
+++ b/drivers/video/msm/mipi_renesas.c
@@ -45,6 +45,9 @@
static char config_PASET[7] = {0x2b, 0x00, 0x00, 0x00, 0x00, 0x03, 0x5f };
static char config_TXON[2] = {0x81, 0x00};
static char config_BLSET_TM[2] = {0xff, 0x6c};
+static char config_DSIRXCTL[2] = {0x41, 0x01};
+static char config_TEON[2] = {0x35, 0x00};
+static char config_TEOFF[1] = {0x34};
static char config_AGCPSCTL_TM[2] = {0x56, 0x08};
@@ -245,7 +248,9 @@
sizeof(config_Power_Ctrl_1a_cmd),
config_Power_Ctrl_1a_cmd},
{DTYPE_DCS_WRITE1, 1, 0, 0, RENESAS_CMD_DELAY,
- sizeof(config_DBICSET_15), config_DBICSET_15}
+ sizeof(config_DBICSET_15), config_DBICSET_15},
+ {DTYPE_DCS_LWRITE, 1, 0, 0, RENESAS_CMD_DELAY,
+ sizeof(config_TEOFF), config_TEOFF},
};
static struct dsi_cmd_desc renesas_display_on_cmds[] = {
@@ -289,6 +294,10 @@
sizeof(config_CASET), config_CASET},
{DTYPE_DCS_LWRITE, 1, 0, 0, RENESAS_CMD_DELAY,
sizeof(config_PASET), config_PASET},
+ {DTYPE_DCS_LWRITE, 1, 0, 0, RENESAS_CMD_DELAY,
+ sizeof(config_DSIRXCTL), config_DSIRXCTL},
+ {DTYPE_DCS_WRITE1, 1, 0, 0, RENESAS_CMD_DELAY,
+ sizeof(config_TEON), config_TEON},
{DTYPE_DCS_WRITE, 1, 0, 0, RENESAS_CMD_DELAY,
sizeof(config_TXON), config_TXON},
{DTYPE_DCS_WRITE1, 1, 0, 0, RENESAS_CMD_DELAY,
diff --git a/drivers/video/msm/mipi_renesas_cmd_fwvga_pt.c b/drivers/video/msm/mipi_renesas_cmd_fwvga_pt.c
index ff573a3..796fbd2 100644
--- a/drivers/video/msm/mipi_renesas_cmd_fwvga_pt.c
+++ b/drivers/video/msm/mipi_renesas_cmd_fwvga_pt.c
@@ -104,11 +104,6 @@
#else
pinfo.clk_rate = 152000000;
#endif
-
-#ifdef USE_HW_VSYNC
- pinfo.lcd.vsync_enable = TRUE;
- pinfo.lcd.hw_vsync_mode = TRUE;
-#endif
pinfo.lcd.refx100 = 6000; /* adjust refx100 to prevent tearing */
pinfo.mipi.mode = DSI_CMD_MODE;
@@ -117,13 +112,15 @@
pinfo.mipi.rgb_swap = DSI_RGB_SWAP_RGB;
pinfo.mipi.data_lane0 = TRUE;
#ifdef CONFIG_FB_MSM_MDP303
+ pinfo.lcd.vsync_enable = TRUE;
+ pinfo.lcd.hw_vsync_mode = TRUE;
pinfo.mipi.data_lane1 = TRUE;
pinfo.mipi.t_clk_post = 0x20;
pinfo.mipi.t_clk_pre = 0x2F;
pinfo.mipi.stream = 0; /* dma_p */
pinfo.mipi.mdp_trigger = DSI_CMD_TRIGGER_SW;
pinfo.mipi.dma_trigger = DSI_CMD_TRIGGER_SW;
- pinfo.mipi.te_sel = 0; /* TE from vsync gpio */
+ pinfo.mipi.te_sel = 1; /* TE from vsync gpio */
pinfo.mipi.interleave_max = 1;
pinfo.mipi.insert_dcs_cmd = TRUE;
pinfo.mipi.wr_mem_continue = 0x3c;