)]}'
{
  "commit": "9de98fb4ec4c91597feedc521120c16fca54a5b6",
  "tree": "bb956a3946cf547d82edf854bdfc960126f31c4b",
  "parents": [
    "6bbfd8975cf3b78aadd1513a25bf7b5c04866a6f"
  ],
  "author": {
    "name": "Mark Salter",
    "email": "msalter@redhat.com",
    "time": "Tue Oct 04 11:20:28 2011 -0400"
  },
  "committer": {
    "name": "Mark Salter",
    "email": "msalter@redhat.com",
    "time": "Thu Oct 06 19:48:36 2011 -0400"
  },
  "message": "C6X: DSCR - Device State Configuration Registers\n\nAll SoCs provide an area of device configuration registers called the DSCR. The\nlocation of specific registers as well as their use varies considerably from\nimplementation to implementation. Rather than having to rely on additional\nSoC-specific DSCR code for each new supported SoC, this code generalize things\nas much as possible using device tree properties. Initialization must take\nplace early on (setup_arch time) in case the event timer device needs to be\nenable via the DSCR.\n\nSigned-off-by: Mark Salter \u003cmsalter@redhat.com\u003e\nSigned-off-by: Aurelien Jacquiot \u003ca-jacquiot@ti.com\u003e\nAcked-by: Arnd Bergmann \u003carnd@arndb.de\u003e\n",
  "tree_diff": [
    {
      "type": "add",
      "old_id": "0000000000000000000000000000000000000000",
      "old_mode": 0,
      "old_path": "/dev/null",
      "new_id": "561ba8332042e032815904ac6fd3c8eff8f82f28",
      "new_mode": 33188,
      "new_path": "arch/c6x/include/asm/dscr.h"
    },
    {
      "type": "add",
      "old_id": "0000000000000000000000000000000000000000",
      "old_mode": 0,
      "old_path": "/dev/null",
      "new_id": "f848a65ee64687608903b2e7a8eb55fcb719950b",
      "new_mode": 33188,
      "new_path": "arch/c6x/platforms/dscr.c"
    }
  ]
}