msm: clock: Support full division range on audio bit clocks
Most of the audio clocks support up to div-256 on 8960 and 9615.
Add support for all the division possibilities by using the new
cdiv clocks support. While we're here move the other divider
clock to use cdiv as well.
Change-Id: I3d7769029934d4413402c0bb44a0a6ee94466868
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
diff --git a/arch/arm/mach-msm/clock-8960.c b/arch/arm/mach-msm/clock-8960.c
index 1a3b86a..7de61d4 100644
--- a/arch/arm/mach-msm/clock-8960.c
+++ b/arch/arm/mach-msm/clock-8960.c
@@ -4480,22 +4480,8 @@
}, \
}
-#define F_AIF_BIT(d, s) \
- { \
- .freq_hz = d, \
- .ns_val = (BVAL(14, 14, s) | BVAL(13, 10, (d-1))) \
- }
-static struct clk_freq_tbl clk_tbl_aif_bit[] = {
- F_AIF_BIT(0, 1), /* Use external clock. */
- F_AIF_BIT(1, 0), F_AIF_BIT(2, 0), F_AIF_BIT(3, 0), F_AIF_BIT(4, 0),
- F_AIF_BIT(5, 0), F_AIF_BIT(6, 0), F_AIF_BIT(7, 0), F_AIF_BIT(8, 0),
- F_AIF_BIT(9, 0), F_AIF_BIT(10, 0), F_AIF_BIT(11, 0), F_AIF_BIT(12, 0),
- F_AIF_BIT(13, 0), F_AIF_BIT(14, 0), F_AIF_BIT(15, 0), F_AIF_BIT(16, 0),
- F_END
-};
-
#define CLK_AIF_BIT(i, ns, h_r) \
- struct rcg_clk i##_clk = { \
+ struct cdiv_clk i##_clk = { \
.b = { \
.ctl_reg = ns, \
.en_mask = BIT(15), \
@@ -4503,35 +4489,18 @@
.halt_check = DELAY, \
}, \
.ns_reg = ns, \
- .ns_mask = BM(14, 10), \
- .set_rate = set_rate_nop, \
- .freq_tbl = clk_tbl_aif_bit, \
- .current_freq = &rcg_dummy_freq, \
+ .ext_mask = BIT(14), \
+ .div_offset = 10, \
+ .max_div = 16, \
.c = { \
.dbg_name = #i "_clk", \
- .ops = &clk_ops_rcg_8960, \
+ .ops = &clk_ops_cdiv, \
CLK_INIT(i##_clk.c), \
}, \
}
-#define F_AIF_BIT_D(d, s) \
- { \
- .freq_hz = d, \
- .ns_val = (BVAL(18, 18, s) | BVAL(17, 10, (d-1))) \
- }
-static struct clk_freq_tbl clk_tbl_aif_bit_div[] = {
- F_AIF_BIT_D(0, 1), /* Use external clock. */
- F_AIF_BIT_D(1, 0), F_AIF_BIT_D(2, 0), F_AIF_BIT_D(3, 0),
- F_AIF_BIT_D(4, 0), F_AIF_BIT_D(5, 0), F_AIF_BIT_D(6, 0),
- F_AIF_BIT_D(7, 0), F_AIF_BIT_D(8, 0), F_AIF_BIT_D(9, 0),
- F_AIF_BIT_D(10, 0), F_AIF_BIT_D(11, 0), F_AIF_BIT_D(12, 0),
- F_AIF_BIT_D(13, 0), F_AIF_BIT_D(14, 0), F_AIF_BIT_D(15, 0),
- F_AIF_BIT_D(16, 0),
- F_END
-};
-
#define CLK_AIF_BIT_DIV(i, ns, h_r) \
- struct rcg_clk i##_clk = { \
+ struct cdiv_clk i##_clk = { \
.b = { \
.ctl_reg = ns, \
.en_mask = BIT(19), \
@@ -4539,13 +4508,12 @@
.halt_check = ENABLE, \
}, \
.ns_reg = ns, \
- .ns_mask = BM(18, 10), \
- .set_rate = set_rate_nop, \
- .freq_tbl = clk_tbl_aif_bit_div, \
- .current_freq = &rcg_dummy_freq, \
+ .ext_mask = BIT(18), \
+ .div_offset = 10, \
+ .max_div = 256, \
.c = { \
.dbg_name = #i "_clk", \
- .ops = &clk_ops_rcg_8960, \
+ .ops = &clk_ops_cdiv, \
CLK_INIT(i##_clk.c), \
}, \
}
diff --git a/arch/arm/mach-msm/clock-8x60.c b/arch/arm/mach-msm/clock-8x60.c
index 17052ae..662e9a6 100644
--- a/arch/arm/mach-msm/clock-8x60.c
+++ b/arch/arm/mach-msm/clock-8x60.c
@@ -3106,22 +3106,8 @@
}, \
}
-#define F_AIF_BIT(d, s) \
- { \
- .freq_hz = d, \
- .ns_val = (BVAL(14, 14, s) | BVAL(13, 10, (d-1))) \
- }
-static struct clk_freq_tbl clk_tbl_aif_bit[] = {
- F_AIF_BIT(0, 1), /* Use external clock. */
- F_AIF_BIT(1, 0), F_AIF_BIT(2, 0), F_AIF_BIT(3, 0), F_AIF_BIT(4, 0),
- F_AIF_BIT(5, 0), F_AIF_BIT(6, 0), F_AIF_BIT(7, 0), F_AIF_BIT(8, 0),
- F_AIF_BIT(9, 0), F_AIF_BIT(10, 0), F_AIF_BIT(11, 0), F_AIF_BIT(12, 0),
- F_AIF_BIT(13, 0), F_AIF_BIT(14, 0), F_AIF_BIT(15, 0), F_AIF_BIT(16, 0),
- F_END
-};
-
#define CLK_AIF_BIT(i, ns, h_r) \
- struct rcg_clk i##_clk = { \
+ struct cdiv_clk i##_clk = { \
.b = { \
.ctl_reg = ns, \
.en_mask = BIT(15), \
@@ -3129,13 +3115,12 @@
.halt_check = DELAY, \
}, \
.ns_reg = ns, \
- .ns_mask = BM(14, 10), \
- .set_rate = set_rate_nop, \
- .freq_tbl = clk_tbl_aif_bit, \
- .current_freq = &rcg_dummy_freq, \
+ .ext_mask = BIT(14), \
+ .div_offset = 10, \
+ .max_div = 16, \
.c = { \
.dbg_name = #i "_clk", \
- .ops = &clk_ops_rcg_8x60, \
+ .ops = &clk_ops_cdiv, \
CLK_INIT(i##_clk.c), \
}, \
}
diff --git a/arch/arm/mach-msm/clock-9615.c b/arch/arm/mach-msm/clock-9615.c
index e72cad7..e47981e 100644
--- a/arch/arm/mach-msm/clock-9615.c
+++ b/arch/arm/mach-msm/clock-9615.c
@@ -1211,22 +1211,8 @@
}, \
}
-#define F_AIF_BIT(d, s) \
- { \
- .freq_hz = d, \
- .ns_val = (BVAL(14, 14, s) | BVAL(13, 10, (d-1))) \
- }
-static struct clk_freq_tbl clk_tbl_aif_bit[] = {
- F_AIF_BIT(0, 1), /* Use external clock. */
- F_AIF_BIT(1, 0), F_AIF_BIT(2, 0), F_AIF_BIT(3, 0), F_AIF_BIT(4, 0),
- F_AIF_BIT(5, 0), F_AIF_BIT(6, 0), F_AIF_BIT(7, 0), F_AIF_BIT(8, 0),
- F_AIF_BIT(9, 0), F_AIF_BIT(10, 0), F_AIF_BIT(11, 0), F_AIF_BIT(12, 0),
- F_AIF_BIT(13, 0), F_AIF_BIT(14, 0), F_AIF_BIT(15, 0), F_AIF_BIT(16, 0),
- F_END
-};
-
#define CLK_AIF_BIT(i, ns, h_r) \
- struct rcg_clk i##_clk = { \
+ struct cdiv_clk i##_clk = { \
.b = { \
.ctl_reg = ns, \
.en_mask = BIT(15), \
@@ -1234,35 +1220,18 @@
.halt_check = DELAY, \
}, \
.ns_reg = ns, \
- .ns_mask = BM(14, 10), \
- .set_rate = set_rate_nop, \
- .freq_tbl = clk_tbl_aif_bit, \
- .current_freq = &rcg_dummy_freq, \
+ .ext_mask = BIT(14), \
+ .div_offset = 10, \
+ .max_div = 16, \
.c = { \
.dbg_name = #i "_clk", \
- .ops = &clk_ops_rcg_9615, \
+ .ops = &clk_ops_cdiv, \
CLK_INIT(i##_clk.c), \
}, \
}
-#define F_AIF_BIT_D(d, s) \
- { \
- .freq_hz = d, \
- .ns_val = (BVAL(18, 18, s) | BVAL(17, 10, (d-1))) \
- }
-static struct clk_freq_tbl clk_tbl_aif_bit_div[] = {
- F_AIF_BIT_D(0, 1), /* Use external clock. */
- F_AIF_BIT_D(1, 0), F_AIF_BIT_D(2, 0), F_AIF_BIT_D(3, 0),
- F_AIF_BIT_D(4, 0), F_AIF_BIT_D(5, 0), F_AIF_BIT_D(6, 0),
- F_AIF_BIT_D(7, 0), F_AIF_BIT_D(8, 0), F_AIF_BIT_D(9, 0),
- F_AIF_BIT_D(10, 0), F_AIF_BIT_D(11, 0), F_AIF_BIT_D(12, 0),
- F_AIF_BIT_D(13, 0), F_AIF_BIT_D(14, 0), F_AIF_BIT_D(15, 0),
- F_AIF_BIT_D(16, 0),
- F_END
-};
-
#define CLK_AIF_BIT_DIV(i, ns, h_r) \
- struct rcg_clk i##_clk = { \
+ struct cdiv_clk i##_clk = { \
.b = { \
.ctl_reg = ns, \
.en_mask = BIT(19), \
@@ -1270,13 +1239,12 @@
.halt_check = ENABLE, \
}, \
.ns_reg = ns, \
- .ns_mask = BM(18, 10), \
- .set_rate = set_rate_nop, \
- .freq_tbl = clk_tbl_aif_bit_div, \
- .current_freq = &rcg_dummy_freq, \
+ .ext_mask = BIT(18), \
+ .div_offset = 10, \
+ .max_div = 256, \
.c = { \
.dbg_name = #i "_clk", \
- .ops = &clk_ops_rcg_9615, \
+ .ops = &clk_ops_cdiv, \
CLK_INIT(i##_clk.c), \
}, \
}