msm: Allow conditional L2 flush during power collapse
On existing targets, L2 is flushed every time any of the core executes a
power collapse. This adds latency into the enter path for idle power
collapse. This commit provides a API that would vote for a L2 flush
during power collapse.
Remove invalidating the L1/L2 cache during warmboot. On
Krait/Scorpion processors, the boot loaders code takes care of
invalidating the L1/L2 cache. On A5 processor, L1 is invalidated at reset.
And the L2 cache is invalidated later in the boot process using the L2
cache controller.
Change-Id: Ib63cfefafcc3aa887faa902a9856fbc5eb137075
Signed-off-by: Maheshkumar Sivasubramanian <msivasub@codeaurora.org>
diff --git a/arch/arm/mach-msm/idle.h b/arch/arm/mach-msm/idle.h
index 138db45..753a47c 100644
--- a/arch/arm/mach-msm/idle.h
+++ b/arch/arm/mach-msm/idle.h
@@ -22,7 +22,14 @@
#ifdef CONFIG_CPU_V7
void msm_pm_boot_entry(void);
void msm_pm_write_boot_vector(unsigned int cpu, unsigned long address);
+void msm_pm_set_l2_flush_flag(unsigned int flag);
extern unsigned long msm_pm_pc_pgd;
+#else
+static inline void msm_pm_set_l2_flush_flag(unsigned int flag)
+{
+ /* empty */
+}
#endif
+
#endif