Revert "ARM: cache-l2x0: Save L2CC registers using pl310 save/resume"
This reverts commit f51e94eabc54067ecb3202e6683f860471ce54f1.
This original change causes low throughput and high CPU usage
during iperf tests for mdm9x15
Change-Id: I64cf35d2822b1c223b7bb95f93c38f7e6e70b303
Signed-off-by: Sridhar Parasuram <sridhar@codeaurora.org>
diff --git a/arch/arm/include/asm/hardware/cache-l2x0.h b/arch/arm/include/asm/hardware/cache-l2x0.h
index d665490..df30306 100644
--- a/arch/arm/include/asm/hardware/cache-l2x0.h
+++ b/arch/arm/include/asm/hardware/cache-l2x0.h
@@ -109,8 +109,8 @@
#define L2X0_PREFETCH_CTRL_WRAP8_SHIFT 30
#ifndef __ASSEMBLY__
-extern void l2cc_suspend(void);
-extern void l2cc_resume(int collapsed);
+extern void l2x0_suspend(void);
+extern void l2x0_resume(int collapsed);
extern void l2x0_cache_sync(void);
extern void __init l2x0_init(void __iomem *base, u32 aux_val, u32 aux_mask);
#if defined(CONFIG_CACHE_L2X0) && defined(CONFIG_OF)
diff --git a/arch/arm/mach-msm/pm-8x60.c b/arch/arm/mach-msm/pm-8x60.c
index 43e7032..c237013 100644
--- a/arch/arm/mach-msm/pm-8x60.c
+++ b/arch/arm/mach-msm/pm-8x60.c
@@ -637,9 +637,9 @@
{
bool collapsed = 0;
- l2cc_suspend();
+ l2x0_suspend();
collapsed = msm_pm_collapse();
- l2cc_resume(collapsed);
+ l2x0_resume(collapsed);
return collapsed;
}
diff --git a/arch/arm/mach-msm/pm2.c b/arch/arm/mach-msm/pm2.c
index 4518d7c..4f3c7e4 100644
--- a/arch/arm/mach-msm/pm2.c
+++ b/arch/arm/mach-msm/pm2.c
@@ -1192,7 +1192,7 @@
#endif
#ifdef CONFIG_CACHE_L2X0
- l2cc_suspend();
+ l2x0_suspend();
#endif
collapsed = msm_pm_collapse();
@@ -1217,7 +1217,7 @@
}
#ifdef CONFIG_CACHE_L2X0
- l2cc_resume(collapsed);
+ l2x0_resume(collapsed);
#endif
msm_pm_boot_config_after_pc(smp_processor_id());
@@ -1434,14 +1434,14 @@
#ifdef CONFIG_CACHE_L2X0
if (!cpu_is_msm8625())
- l2cc_suspend();
+ l2x0_suspend();
#endif
collapsed = msm_pm_collapse();
#ifdef CONFIG_CACHE_L2X0
if (!cpu_is_msm8625())
- l2cc_resume(collapsed);
+ l2x0_resume(collapsed);
#endif
msm_pm_boot_config_after_pc(smp_processor_id());
diff --git a/arch/arm/mm/cache-l2x0.c b/arch/arm/mm/cache-l2x0.c
index 2d94030..db2a9b4 100644
--- a/arch/arm/mm/cache-l2x0.c
+++ b/arch/arm/mm/cache-l2x0.c
@@ -30,6 +30,8 @@
#define CACHE_LINE_SIZE 32
static void __iomem *l2x0_base;
+static uint32_t aux_ctrl_save;
+static uint32_t data_latency_ctrl;
static DEFINE_RAW_SPINLOCK(l2x0_lock);
static uint32_t l2x0_way_mask; /* Bitmask of active ways */
@@ -447,6 +449,51 @@
ways, cache_id, aux, l2x0_size);
}
+void l2x0_suspend(void)
+{
+ /* Save aux control register value */
+ aux_ctrl_save = readl_relaxed(l2x0_base + L2X0_AUX_CTRL);
+ data_latency_ctrl = readl_relaxed(l2x0_base + L2X0_DATA_LATENCY_CTRL);
+ /* Flush all cache */
+ l2x0_flush_all();
+ /* Disable the cache */
+ writel_relaxed(0, l2x0_base + L2X0_CTRL);
+
+ /* Memory barrier */
+ dmb();
+}
+
+void l2x0_resume(int collapsed)
+{
+ if (collapsed) {
+ /* Disable the cache */
+ writel_relaxed(0, l2x0_base + L2X0_CTRL);
+
+ /* Restore aux control register value */
+ writel_relaxed(aux_ctrl_save, l2x0_base + L2X0_AUX_CTRL);
+ writel_relaxed(data_latency_ctrl, l2x0_base +
+ L2X0_DATA_LATENCY_CTRL);
+
+ /* Invalidate the cache */
+ l2x0_inv_all();
+ /*
+ * TBD: make sure that l2xo_inv_all finished
+ * before actually enabling the cache. Logically this
+ * is not required as cache sync is atomic operation.
+ * but on 8x25, observed the random crashes and they go
+ * away if we add dmb or disable the L2.
+ * keeping this as temporary workaround until root
+ * cause is find out.
+ */
+ dmb();
+ }
+
+ /* Enable the cache */
+ writel_relaxed(1, l2x0_base + L2X0_CTRL);
+
+ mb();
+}
+
#ifdef CONFIG_OF
static void __init l2x0_of_setup(const struct device_node *np,
u32 *aux_val, u32 *aux_mask)
@@ -515,7 +562,6 @@
l2x0_base + L2X0_ADDR_FILTER_START);
}
}
-#endif
static void pl310_save(void)
{
@@ -591,7 +637,6 @@
l2x0_resume();
}
-#ifdef CONFIG_OF
static const struct l2x0_of_data pl310_data = {
pl310_of_setup,
pl310_save,
@@ -647,17 +692,3 @@
return 0;
}
#endif
-
-void l2cc_suspend(void)
-{
- pl310_save();
- l2x0_disable();
- dmb();
-}
-
-void l2cc_resume(int collapsed)
-{
- if (collapsed)
- pl310_resume();
- dmb();
-}