msm: acpuclock-krait: Keep the secondary MUX input fixed
With use of the QSB clock source recently eliminated, only one
input of the secondary clock MUX is used on any target. Since
there is overhead involved reprogramming this MUX when changing
the CPU and L2 frequencies, change the code to just program the
MUX at boot. Most noticeably, this removes a 1us delay from
every CPU and L2 frequency switch.
Signed-off-by: Matt Wagantall <mattw@codeaurora.org>
Conflicts:
arch/arm/mach-msm/acpuclock-8064.c
Change-Id: I404913cec05f8893e08bf3f8d0c0f691c8d0f7d9
Signed-off-by: Neha Pandey <nehap@codeaurora.org>
diff --git a/arch/arm/mach-msm/acpuclock-8627.c b/arch/arm/mach-msm/acpuclock-8627.c
index 9e6662d..da49656 100644
--- a/arch/arm/mach-msm/acpuclock-8627.c
+++ b/arch/arm/mach-msm/acpuclock-8627.c
@@ -50,6 +50,7 @@
.hfpll_phys_base = 0x00903200,
.aux_clk_sel_phys = 0x02088014,
.aux_clk_sel = 3,
+ .sec_clk_sel = 2,
.l2cpmr_iaddr = 0x4501,
.vreg[VREG_CORE] = { "krait0", 1300000 },
.vreg[VREG_MEM] = { "krait0_mem", 1150000 },
@@ -60,6 +61,7 @@
.hfpll_phys_base = 0x00903300,
.aux_clk_sel_phys = 0x02098014,
.aux_clk_sel = 3,
+ .sec_clk_sel = 2,
.l2cpmr_iaddr = 0x5501,
.vreg[VREG_CORE] = { "krait1", 1300000 },
.vreg[VREG_MEM] = { "krait1_mem", 1150000 },
@@ -70,6 +72,7 @@
.hfpll_phys_base = 0x00903400,
.aux_clk_sel_phys = 0x02011028,
.aux_clk_sel = 3,
+ .sec_clk_sel = 2,
.l2cpmr_iaddr = 0x0500,
.vreg[VREG_HFPLL_A] = { "l2_hfpll", 1800000 },
},
@@ -92,35 +95,35 @@
/* TODO: Update vdd_dig, vdd_mem and bw when data is available. */
static struct l2_level l2_freq_tbl[] __initdata = {
- [0] = { { 384000, PLL_8, 0, 2, 0x00 }, LVL_NOM, 1050000, 1 },
- [1] = { { 432000, HFPLL, 2, 0, 0x20 }, LVL_NOM, 1050000, 1 },
- [2] = { { 486000, HFPLL, 2, 0, 0x24 }, LVL_NOM, 1050000, 1 },
- [3] = { { 540000, HFPLL, 2, 0, 0x28 }, LVL_NOM, 1050000, 2 },
- [4] = { { 594000, HFPLL, 1, 0, 0x16 }, LVL_NOM, 1050000, 2 },
- [5] = { { 648000, HFPLL, 1, 0, 0x18 }, LVL_NOM, 1050000, 2 },
- [6] = { { 702000, HFPLL, 1, 0, 0x1A }, LVL_NOM, 1050000, 3 },
- [7] = { { 756000, HFPLL, 1, 0, 0x1C }, LVL_HIGH, 1150000, 3 },
- [8] = { { 810000, HFPLL, 1, 0, 0x1E }, LVL_HIGH, 1150000, 3 },
- [9] = { { 864000, HFPLL, 1, 0, 0x20 }, LVL_HIGH, 1150000, 4 },
- [10] = { { 918000, HFPLL, 1, 0, 0x22 }, LVL_HIGH, 1150000, 4 },
- [11] = { { 972000, HFPLL, 1, 0, 0x24 }, LVL_HIGH, 1150000, 4 },
+ [0] = { { 384000, PLL_8, 0, 0x00 }, LVL_NOM, 1050000, 1 },
+ [1] = { { 432000, HFPLL, 2, 0x20 }, LVL_NOM, 1050000, 1 },
+ [2] = { { 486000, HFPLL, 2, 0x24 }, LVL_NOM, 1050000, 1 },
+ [3] = { { 540000, HFPLL, 2, 0x28 }, LVL_NOM, 1050000, 2 },
+ [4] = { { 594000, HFPLL, 1, 0x16 }, LVL_NOM, 1050000, 2 },
+ [5] = { { 648000, HFPLL, 1, 0x18 }, LVL_NOM, 1050000, 2 },
+ [6] = { { 702000, HFPLL, 1, 0x1A }, LVL_NOM, 1050000, 3 },
+ [7] = { { 756000, HFPLL, 1, 0x1C }, LVL_HIGH, 1150000, 3 },
+ [8] = { { 810000, HFPLL, 1, 0x1E }, LVL_HIGH, 1150000, 3 },
+ [9] = { { 864000, HFPLL, 1, 0x20 }, LVL_HIGH, 1150000, 4 },
+ [10] = { { 918000, HFPLL, 1, 0x22 }, LVL_HIGH, 1150000, 4 },
+ [11] = { { 972000, HFPLL, 1, 0x24 }, LVL_HIGH, 1150000, 4 },
{ }
};
/* TODO: Update core voltages when data is available. */
static struct acpu_level acpu_freq_tbl[] __initdata = {
- { 1, { 384000, PLL_8, 0, 2, 0x00 }, L2(0), 900000 },
- { 1, { 432000, HFPLL, 2, 0, 0x20 }, L2(4), 925000 },
- { 1, { 486000, HFPLL, 2, 0, 0x24 }, L2(4), 925000 },
- { 1, { 540000, HFPLL, 2, 0, 0x28 }, L2(4), 937500 },
- { 1, { 594000, HFPLL, 1, 0, 0x16 }, L2(4), 962500 },
- { 1, { 648000, HFPLL, 1, 0, 0x18 }, L2(8), 987500 },
- { 1, { 702000, HFPLL, 1, 0, 0x1A }, L2(8), 1000000 },
- { 1, { 756000, HFPLL, 1, 0, 0x1C }, L2(8), 1025000 },
- { 1, { 810000, HFPLL, 1, 0, 0x1E }, L2(8), 1062500 },
- { 1, { 864000, HFPLL, 1, 0, 0x20 }, L2(11), 1062500 },
- { 1, { 918000, HFPLL, 1, 0, 0x22 }, L2(11), 1087500 },
- { 1, { 972000, HFPLL, 1, 0, 0x24 }, L2(11), 1100000 },
+ { 1, { 384000, PLL_8, 0, 0x00 }, L2(0), 900000 },
+ { 1, { 432000, HFPLL, 2, 0x20 }, L2(4), 925000 },
+ { 1, { 486000, HFPLL, 2, 0x24 }, L2(4), 925000 },
+ { 1, { 540000, HFPLL, 2, 0x28 }, L2(4), 937500 },
+ { 1, { 594000, HFPLL, 1, 0x16 }, L2(4), 962500 },
+ { 1, { 648000, HFPLL, 1, 0x18 }, L2(8), 987500 },
+ { 1, { 702000, HFPLL, 1, 0x1A }, L2(8), 1000000 },
+ { 1, { 756000, HFPLL, 1, 0x1C }, L2(8), 1025000 },
+ { 1, { 810000, HFPLL, 1, 0x1E }, L2(8), 1062500 },
+ { 1, { 864000, HFPLL, 1, 0x20 }, L2(11), 1062500 },
+ { 1, { 918000, HFPLL, 1, 0x22 }, L2(11), 1087500 },
+ { 1, { 972000, HFPLL, 1, 0x24 }, L2(11), 1100000 },
{ 0, { 0 } }
};