msm: acpuclock-krait: Keep the secondary MUX input fixed
With use of the QSB clock source recently eliminated, only one
input of the secondary clock MUX is used on any target. Since
there is overhead involved reprogramming this MUX when changing
the CPU and L2 frequencies, change the code to just program the
MUX at boot. Most noticeably, this removes a 1us delay from
every CPU and L2 frequency switch.
Signed-off-by: Matt Wagantall <mattw@codeaurora.org>
Conflicts:
arch/arm/mach-msm/acpuclock-8064.c
Change-Id: I404913cec05f8893e08bf3f8d0c0f691c8d0f7d9
Signed-off-by: Neha Pandey <nehap@codeaurora.org>
diff --git a/arch/arm/mach-msm/acpuclock-8960ab.c b/arch/arm/mach-msm/acpuclock-8960ab.c
index 628e1ba..91ccd37 100644
--- a/arch/arm/mach-msm/acpuclock-8960ab.c
+++ b/arch/arm/mach-msm/acpuclock-8960ab.c
@@ -44,6 +44,7 @@
.hfpll_phys_base = 0x00903200,
.aux_clk_sel_phys = 0x02088014,
.aux_clk_sel = 3,
+ .sec_clk_sel = 2,
.l2cpmr_iaddr = 0x4501,
.vreg[VREG_CORE] = { "krait0", 1300000 },
.vreg[VREG_MEM] = { "krait0_mem", 1150000 },
@@ -55,6 +56,7 @@
.hfpll_phys_base = 0x00903300,
.aux_clk_sel_phys = 0x02098014,
.aux_clk_sel = 3,
+ .sec_clk_sel = 2,
.l2cpmr_iaddr = 0x5501,
.vreg[VREG_CORE] = { "krait1", 1300000 },
.vreg[VREG_MEM] = { "krait1_mem", 1150000 },
@@ -66,6 +68,7 @@
.hfpll_phys_base = 0x00903400,
.aux_clk_sel_phys = 0x02011028,
.aux_clk_sel = 3,
+ .sec_clk_sel = 2,
.l2cpmr_iaddr = 0x0500,
.vreg[VREG_HFPLL_A] = { "l2_s8", 2050000 },
.vreg[VREG_HFPLL_B] = { "l2_l23", 1800000 },
@@ -89,46 +92,46 @@
};
static struct l2_level l2_freq_tbl[] __initdata = {
- [0] = { { 384000, PLL_8, 0, 2, 0x00 }, 1050000, 1050000, 1 },
- [1] = { { 486000, HFPLL, 2, 0, 0x24 }, 1050000, 1050000, 2 },
- [2] = { { 594000, HFPLL, 1, 0, 0x16 }, 1050000, 1050000, 2 },
- [3] = { { 702000, HFPLL, 1, 0, 0x1A }, 1050000, 1050000, 4 },
- [4] = { { 810000, HFPLL, 1, 0, 0x1E }, 1050000, 1050000, 4 },
- [5] = { { 918000, HFPLL, 1, 0, 0x22 }, 1150000, 1150000, 5 },
- [6] = { { 1026000, HFPLL, 1, 0, 0x26 }, 1150000, 1150000, 5 },
- [7] = { { 1134000, HFPLL, 1, 0, 0x2A }, 1150000, 1150000, 5 },
- [8] = { { 1242000, HFPLL, 1, 0, 0x2E }, 1150000, 1150000, 5 },
- [9] = { { 1350000, HFPLL, 1, 0, 0x32 }, 1150000, 1150000, 5 },
+ [0] = { { 384000, PLL_8, 0, 0x00 }, 1050000, 1050000, 1 },
+ [1] = { { 486000, HFPLL, 2, 0x24 }, 1050000, 1050000, 2 },
+ [2] = { { 594000, HFPLL, 1, 0x16 }, 1050000, 1050000, 2 },
+ [3] = { { 702000, HFPLL, 1, 0x1A }, 1050000, 1050000, 4 },
+ [4] = { { 810000, HFPLL, 1, 0x1E }, 1050000, 1050000, 4 },
+ [5] = { { 918000, HFPLL, 1, 0x22 }, 1150000, 1150000, 5 },
+ [6] = { { 1026000, HFPLL, 1, 0x26 }, 1150000, 1150000, 5 },
+ [7] = { { 1134000, HFPLL, 1, 0x2A }, 1150000, 1150000, 5 },
+ [8] = { { 1242000, HFPLL, 1, 0x2E }, 1150000, 1150000, 5 },
+ [9] = { { 1350000, HFPLL, 1, 0x32 }, 1150000, 1150000, 5 },
{ }
};
static struct acpu_level acpu_freq_tbl_slow[] __initdata = {
- { 1, { 384000, PLL_8, 0, 2, 0x00 }, L2(0), 950000 },
- { 0, { 432000, HFPLL, 2, 0, 0x20 }, L2(3), 975000 },
- { 1, { 486000, HFPLL, 2, 0, 0x24 }, L2(3), 975000 },
- { 0, { 540000, HFPLL, 2, 0, 0x28 }, L2(3), 1000000 },
- { 1, { 594000, HFPLL, 1, 0, 0x16 }, L2(3), 1000000 },
- { 0, { 648000, HFPLL, 1, 0, 0x18 }, L2(3), 1025000 },
- { 1, { 702000, HFPLL, 1, 0, 0x1A }, L2(3), 1025000 },
- { 0, { 756000, HFPLL, 1, 0, 0x1C }, L2(3), 1075000 },
- { 1, { 810000, HFPLL, 1, 0, 0x1E }, L2(3), 1075000 },
- { 0, { 864000, HFPLL, 1, 0, 0x20 }, L2(3), 1100000 },
- { 1, { 918000, HFPLL, 1, 0, 0x22 }, L2(3), 1100000 },
- { 0, { 972000, HFPLL, 1, 0, 0x24 }, L2(3), 1125000 },
- { 1, { 1026000, HFPLL, 1, 0, 0x26 }, L2(3), 1125000 },
- { 0, { 1080000, HFPLL, 1, 0, 0x28 }, L2(9), 1175000 },
- { 1, { 1134000, HFPLL, 1, 0, 0x2A }, L2(9), 1175000 },
- { 0, { 1188000, HFPLL, 1, 0, 0x2C }, L2(9), 1200000 },
- { 1, { 1242000, HFPLL, 1, 0, 0x2E }, L2(9), 1200000 },
- { 0, { 1296000, HFPLL, 1, 0, 0x30 }, L2(9), 1225000 },
- { 1, { 1350000, HFPLL, 1, 0, 0x32 }, L2(9), 1225000 },
- { 0, { 1404000, HFPLL, 1, 0, 0x34 }, L2(9), 1237500 },
- { 1, { 1458000, HFPLL, 1, 0, 0x36 }, L2(9), 1237500 },
- { 1, { 1512000, HFPLL, 1, 0, 0x38 }, L2(9), 1250000 },
- { 1, { 1566000, HFPLL, 1, 0, 0x3A }, L2(9), 1250000 },
- { 1, { 1620000, HFPLL, 1, 0, 0x3C }, L2(9), 1250000 },
- { 1, { 1674000, HFPLL, 1, 0, 0x3E }, L2(9), 1250000 },
- { 1, { 1728000, HFPLL, 1, 0, 0x40 }, L2(9), 1250000 },
+ { 1, { 384000, PLL_8, 0, 0x00 }, L2(0), 950000 },
+ { 0, { 432000, HFPLL, 2, 0x20 }, L2(3), 975000 },
+ { 1, { 486000, HFPLL, 2, 0x24 }, L2(3), 975000 },
+ { 0, { 540000, HFPLL, 2, 0x28 }, L2(3), 1000000 },
+ { 1, { 594000, HFPLL, 1, 0x16 }, L2(3), 1000000 },
+ { 0, { 648000, HFPLL, 1, 0x18 }, L2(3), 1025000 },
+ { 1, { 702000, HFPLL, 1, 0x1A }, L2(3), 1025000 },
+ { 0, { 756000, HFPLL, 1, 0x1C }, L2(3), 1075000 },
+ { 1, { 810000, HFPLL, 1, 0x1E }, L2(3), 1075000 },
+ { 0, { 864000, HFPLL, 1, 0x20 }, L2(3), 1100000 },
+ { 1, { 918000, HFPLL, 1, 0x22 }, L2(3), 1100000 },
+ { 0, { 972000, HFPLL, 1, 0x24 }, L2(3), 1125000 },
+ { 1, { 1026000, HFPLL, 1, 0x26 }, L2(3), 1125000 },
+ { 0, { 1080000, HFPLL, 1, 0x28 }, L2(9), 1175000 },
+ { 1, { 1134000, HFPLL, 1, 0x2A }, L2(9), 1175000 },
+ { 0, { 1188000, HFPLL, 1, 0x2C }, L2(9), 1200000 },
+ { 1, { 1242000, HFPLL, 1, 0x2E }, L2(9), 1200000 },
+ { 0, { 1296000, HFPLL, 1, 0x30 }, L2(9), 1225000 },
+ { 1, { 1350000, HFPLL, 1, 0x32 }, L2(9), 1225000 },
+ { 0, { 1404000, HFPLL, 1, 0x34 }, L2(9), 1237500 },
+ { 1, { 1458000, HFPLL, 1, 0x36 }, L2(9), 1237500 },
+ { 1, { 1512000, HFPLL, 1, 0x38 }, L2(9), 1250000 },
+ { 1, { 1566000, HFPLL, 1, 0x3A }, L2(9), 1250000 },
+ { 1, { 1620000, HFPLL, 1, 0x3C }, L2(9), 1250000 },
+ { 1, { 1674000, HFPLL, 1, 0x3E }, L2(9), 1250000 },
+ { 1, { 1728000, HFPLL, 1, 0x40 }, L2(9), 1250000 },
{ 0, { 0 } }
};