msm: acpuclock-krait: Keep the secondary MUX input fixed
With use of the QSB clock source recently eliminated, only one
input of the secondary clock MUX is used on any target. Since
there is overhead involved reprogramming this MUX when changing
the CPU and L2 frequencies, change the code to just program the
MUX at boot. Most noticeably, this removes a 1us delay from
every CPU and L2 frequency switch.
Signed-off-by: Matt Wagantall <mattw@codeaurora.org>
Conflicts:
arch/arm/mach-msm/acpuclock-8064.c
Change-Id: I404913cec05f8893e08bf3f8d0c0f691c8d0f7d9
Signed-off-by: Neha Pandey <nehap@codeaurora.org>
diff --git a/arch/arm/mach-msm/acpuclock-krait.c b/arch/arm/mach-msm/acpuclock-krait.c
index 1ac082f..5c7e565 100644
--- a/arch/arm/mach-msm/acpuclock-krait.c
+++ b/arch/arm/mach-msm/acpuclock-krait.c
@@ -42,8 +42,6 @@
#define PRI_SRC_SEL_SEC_SRC 0
#define PRI_SRC_SEL_HFPLL 1
#define PRI_SRC_SEL_HFPLL_DIV2 2
-#define SEC_SRC_SEL_L2PLL 1
-#define SEC_SRC_SEL_AUX 2
static DEFINE_MUTEX(driver_lock);
static DEFINE_SPINLOCK(l2_lock);
@@ -79,7 +77,7 @@
}
/* Select a source on the secondary MUX. */
-static void set_sec_clk_src(struct scalable *sc, u32 sec_src_sel)
+static void __cpuinit set_sec_clk_src(struct scalable *sc, u32 sec_src_sel)
{
u32 regval;
@@ -220,7 +218,6 @@
* Move to an always-on source running at a frequency
* that does not require an elevated CPU voltage.
*/
- set_sec_clk_src(sc, SEC_SRC_SEL_AUX);
set_pri_clk_src(sc, PRI_SRC_SEL_SEC_SRC);
/* Re-program HFPLL. */
@@ -231,15 +228,12 @@
/* Move to HFPLL. */
set_pri_clk_src(sc, tgt_s->pri_src_sel);
} else if (strt_s->src == HFPLL && tgt_s->src != HFPLL) {
- set_sec_clk_src(sc, tgt_s->sec_src_sel);
set_pri_clk_src(sc, tgt_s->pri_src_sel);
hfpll_disable(sc, false);
} else if (strt_s->src != HFPLL && tgt_s->src == HFPLL) {
hfpll_set_rate(sc, tgt_s);
hfpll_enable(sc, false);
set_pri_clk_src(sc, tgt_s->pri_src_sel);
- } else {
- set_sec_clk_src(sc, tgt_s->sec_src_sel);
}
sc->cur_speed = tgt_s;
@@ -709,7 +703,7 @@
}
/* Switch away from the HFPLL while it's re-initialized. */
- set_sec_clk_src(sc, SEC_SRC_SEL_AUX);
+ set_sec_clk_src(sc, sc->sec_clk_sel);
set_pri_clk_src(sc, PRI_SRC_SEL_SEC_SRC);
hfpll_init(sc, tgt_s);
@@ -719,7 +713,6 @@
set_l2_indirect_reg(sc->l2cpmr_iaddr, regval);
/* Switch to the target clock source. */
- set_sec_clk_src(sc, tgt_s->sec_src_sel);
set_pri_clk_src(sc, tgt_s->pri_src_sel);
sc->cur_speed = tgt_s;
@@ -730,7 +723,6 @@
struct scalable *sc)
{
s->pri_src_sel = get_l2_indirect_reg(sc->l2cpmr_iaddr) & 0x3;
- s->sec_src_sel = (get_l2_indirect_reg(sc->l2cpmr_iaddr) >> 2) & 0x3;
s->pll_l_val = readl_relaxed(sc->hfpll_base + drv.hfpll_data->l_offset);
}
@@ -738,7 +730,6 @@
const struct core_speed *s2)
{
return (s1->pri_src_sel == s2->pri_src_sel &&
- s1->sec_src_sel == s2->sec_src_sel &&
s1->pll_l_val == s2->pll_l_val);
}