msm: platsmp-8625: Clear the IPC1 pending interrupt in the CORE1 context
Once core0 comes out of the PC, it uses the IPC1 interrupt to wake up
the core1 out of the sleep(GDFS). Since this interrupt is intended to
core1, move the clearing of this interrupt from core0 to core1 context.
Remove the masking and umnaking of IPC1, as no other driver is going
to use this interupt.
Change-Id: I2b3919a69e4c6c0d8f1eec60b3af812f42ba7cd7
Signed-off-by: Murali Nalajala <mnalajal@codeaurora.org>
diff --git a/arch/arm/mach-msm/platsmp-8625.c b/arch/arm/mach-msm/platsmp-8625.c
index 82aeb16..23ca454 100644
--- a/arch/arm/mach-msm/platsmp-8625.c
+++ b/arch/arm/mach-msm/platsmp-8625.c
@@ -120,16 +120,11 @@
raw_spin_unlock(&irq_controller_lock);
}
-void clear_pending_spi(unsigned int irq)
+static void clear_pending_spi(unsigned int irq)
{
- struct irq_data *d = irq_get_irq_data(irq);
- struct irq_chip *c = irq_data_get_irq_chip(d);
-
/* Clear the IRQ from the ENABLE_SET */
- c->irq_mask(d);
local_irq_disable();
gic_clear_spi_pending(irq);
- c->irq_unmask(d);
local_irq_enable();
}
@@ -152,6 +147,13 @@
*/
write_pen_release(-1);
+ /* clear the IPC1(SPI-8) pending SPI */
+ if (power_collapsed) {
+ raise_clear_spi(1, false);
+ clear_pending_spi(MSM8625_INT_ACSR_MP_CORE_IPC1);
+ power_collapsed = 0;
+ }
+
/*
* Synchronise with the boot thread.
*/
@@ -246,13 +248,6 @@
udelay(10);
}
- /* Now we should clear the pending SPI */
- if (power_collapsed) {
- raise_clear_spi(1, false);
- clear_pending_spi(MSM8625_INT_ACSR_MP_CORE_IPC1);
- power_collapsed = 0;
- }
-
/*
* now the secondary core is starting up let it run its
* calibrations, then wait for it to finish