msm: acpuclock-8974: Update HFPLL configuration
The HFPLL configuration recommended by the hardware designers has been
updated. Update acpuclock to match.
In addition to changes to the static register configuration, runtime
selection of the correct VCO mode is required. For frequencies above
1248MHz, the high-frequency VCO mode is used. The low-frequency mode
is used for frequencies below that.
Change-Id: Ib0585b5262d27791128a54910b75d2dc0c581775
Signed-off-by: Matt Wagantall <mattw@codeaurora.org>
diff --git a/arch/arm/mach-msm/acpuclock-8974.c b/arch/arm/mach-msm/acpuclock-8974.c
index 9555fd24..c7800fc 100644
--- a/arch/arm/mach-msm/acpuclock-8974.c
+++ b/arch/arm/mach-msm/acpuclock-8974.c
@@ -33,9 +33,13 @@
.l_offset = 0x04,
.m_offset = 0x08,
.n_offset = 0x0C,
+ .has_user_reg = true,
+ .user_offset = 0x10,
.config_offset = 0x14,
- /* TODO: Verify magic number for 8974 when available. */
- .config_val = 0x7845C665,
+ /* TODO: Verify magic numbers when final values are available. */
+ .user_val = 0x8,
+ .config_val = 0x04D0405D,
+ .low_vco_l_max = 65,
.low_vdd_l_max = 52,
.nom_vdd_l_max = 104,
.vdd[HFPLL_VDD_NONE] = LVL_NONE,
diff --git a/arch/arm/mach-msm/acpuclock-krait.c b/arch/arm/mach-msm/acpuclock-krait.c
index 79922e6..070ce71 100644
--- a/arch/arm/mach-msm/acpuclock-krait.c
+++ b/arch/arm/mach-msm/acpuclock-krait.c
@@ -170,8 +170,19 @@
/* Program the HFPLL rate. Assumes HFPLL is already disabled. */
static void hfpll_set_rate(struct scalable *sc, const struct core_speed *tgt_s)
{
- writel_relaxed(tgt_s->pll_l_val,
- sc->hfpll_base + drv.hfpll_data->l_offset);
+ void __iomem *base = sc->hfpll_base;
+ u32 regval;
+
+ writel_relaxed(tgt_s->pll_l_val, base + drv.hfpll_data->l_offset);
+
+ if (drv.hfpll_data->has_user_reg) {
+ regval = readl_relaxed(base + drv.hfpll_data->user_offset);
+ if (tgt_s->pll_l_val <= drv.hfpll_data->low_vco_l_max)
+ regval &= ~drv.hfpll_data->user_vco_mask;
+ else
+ regval |= drv.hfpll_data->user_vco_mask;
+ writel_relaxed(regval, base + drv.hfpll_data->user_offset);
+ }
}
/* Return the L2 speed that should be applied. */
@@ -513,6 +524,9 @@
sc->hfpll_base + drv.hfpll_data->config_offset);
writel_relaxed(0, sc->hfpll_base + drv.hfpll_data->m_offset);
writel_relaxed(1, sc->hfpll_base + drv.hfpll_data->n_offset);
+ if (drv.hfpll_data->has_user_reg)
+ writel_relaxed(drv.hfpll_data->user_val,
+ sc->hfpll_base + drv.hfpll_data->user_offset);
/* Program droop controller, if supported */
if (drv.hfpll_data->has_droop_ctl)
diff --git a/arch/arm/mach-msm/acpuclock-krait.h b/arch/arm/mach-msm/acpuclock-krait.h
index d9aca5c..0b304ec 100644
--- a/arch/arm/mach-msm/acpuclock-krait.h
+++ b/arch/arm/mach-msm/acpuclock-krait.h
@@ -162,11 +162,16 @@
* @n_offset: "N" value register offset from base address.
* @config_offset: Configuration register offset from base address.
* @config_val: Value to initialize the @config_offset register to.
+ * @has_user_reg: Indicates the presence of an addition config register.
+ * @user_offset: User register offset from base address, if applicable.
+ * @user_val: Value to initialize the @user_offset register to.
+ * @user_vco_mask: Bit in the @user_offset to enable high-frequency VCO mode.
* @has_droop_ctl: Indicates the presence of a voltage droop controller.
* @droop_offset: Droop controller register offset from base address.
* @droop_val: Value to initialize the @config_offset register to.
* @low_vdd_l_max: Maximum "L" value supported at HFPLL_VDD_LOW.
* @nom_vdd_l_max: Maximum "L" value supported at HFPLL_VDD_NOM.
+ * @low_vco_l_max: Maximum "L" value supported in low-frequency VCO mode.
* @vdd: voltage requirements for each VDD level for the L2 PLL.
*/
struct hfpll_data {
@@ -176,11 +181,16 @@
const u32 n_offset;
const u32 config_offset;
const u32 config_val;
+ const bool has_user_reg;
+ const u32 user_offset;
+ const u32 user_val;
+ const u32 user_vco_mask;
const bool has_droop_ctl;
const u32 droop_offset;
const u32 droop_val;
const u32 low_vdd_l_max;
const u32 nom_vdd_l_max;
+ const u32 low_vco_l_max;
const int vdd[NUM_HFPLL_VDD];
};