| /* Copyright (c) 2008-2011, Code Aurora Forum. All rights reserved. |
| * |
| * This program is free software; you can redistribute it and/or modify |
| * it under the terms of the GNU General Public License version 2 and |
| * only version 2 as published by the Free Software Foundation. |
| * |
| * This program is distributed in the hope that it will be useful, |
| * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| * GNU General Public License for more details. |
| * |
| */ |
| #ifndef __ADRENO_H |
| #define __ADRENO_H |
| |
| #include "kgsl_device.h" |
| #include "adreno_drawctxt.h" |
| #include "adreno_ringbuffer.h" |
| |
| #define DEVICE_3D_NAME "kgsl-3d" |
| #define DEVICE_3D0_NAME "kgsl-3d0" |
| |
| #define ADRENO_DEVICE(device) \ |
| KGSL_CONTAINER_OF(device, struct adreno_device, dev) |
| |
| /* Flags to control command packet settings */ |
| #define KGSL_CMD_FLAGS_PMODE 0x00000001 |
| #define KGSL_CMD_FLAGS_NO_TS_CMP 0x00000002 |
| #define KGSL_CMD_FLAGS_NOT_KERNEL_CMD 0x00000004 |
| |
| /* Command identifiers */ |
| #define KGSL_CONTEXT_TO_MEM_IDENTIFIER 0xDEADBEEF |
| #define KGSL_CMD_IDENTIFIER 0xFEEDFACE |
| |
| #ifdef CONFIG_MSM_SCM |
| #define ADRENO_DEFAULT_PWRSCALE_POLICY (&kgsl_pwrscale_policy_tz) |
| #else |
| #define ADRENO_DEFAULT_PWRSCALE_POLICY NULL |
| #endif |
| |
| enum adreno_gpurev { |
| ADRENO_REV_UNKNOWN = 0, |
| ADRENO_REV_A200 = 200, |
| ADRENO_REV_A205 = 205, |
| ADRENO_REV_A220 = 220, |
| ADRENO_REV_A225 = 225, |
| }; |
| |
| struct adreno_gpudev; |
| |
| struct adreno_device { |
| struct kgsl_device dev; /* Must be first field in this struct */ |
| unsigned int chip_id; |
| enum adreno_gpurev gpurev; |
| struct kgsl_memregion gmemspace; |
| struct adreno_context *drawctxt_active; |
| wait_queue_head_t ib1_wq; |
| unsigned int *pfp_fw; |
| size_t pfp_fw_size; |
| unsigned int *pm4_fw; |
| size_t pm4_fw_size; |
| struct adreno_ringbuffer ringbuffer; |
| unsigned int mharb; |
| struct adreno_gpudev *gpudev; |
| }; |
| |
| struct adreno_gpudev { |
| int (*ctxt_gpustate_shadow)(struct adreno_device *, |
| struct adreno_context *); |
| int (*ctxt_gmem_shadow)(struct adreno_device *, |
| struct adreno_context *); |
| void (*ctxt_save)(struct adreno_device *, struct adreno_context *); |
| void (*ctxt_restore)(struct adreno_device *, struct adreno_context *); |
| irqreturn_t (*irq_handler)(struct adreno_device *); |
| void (*irq_control)(struct adreno_device *, int); |
| }; |
| |
| extern struct adreno_gpudev adreno_a2xx_gpudev; |
| |
| int adreno_idle(struct kgsl_device *device, unsigned int timeout); |
| void adreno_regread(struct kgsl_device *device, unsigned int offsetwords, |
| unsigned int *value); |
| void adreno_regwrite(struct kgsl_device *device, unsigned int offsetwords, |
| unsigned int value); |
| |
| uint8_t *kgsl_sharedmem_convertaddr(struct kgsl_device *device, |
| unsigned int pt_base, unsigned int gpuaddr, unsigned int *size); |
| |
| static inline int adreno_is_a200(struct adreno_device *adreno_dev) |
| { |
| return (adreno_dev->gpurev == ADRENO_REV_A200); |
| } |
| |
| static inline int adreno_is_a205(struct adreno_device *adreno_dev) |
| { |
| return (adreno_dev->gpurev == ADRENO_REV_A200); |
| } |
| |
| static inline int adreno_is_a20x(struct adreno_device *adreno_dev) |
| { |
| return (adreno_dev->gpurev == ADRENO_REV_A200 || |
| adreno_dev->gpurev == ADRENO_REV_A205); |
| } |
| |
| static inline int adreno_is_a220(struct adreno_device *adreno_dev) |
| { |
| return (adreno_dev->gpurev == ADRENO_REV_A220); |
| } |
| |
| static inline int adreno_is_a225(struct adreno_device *adreno_dev) |
| { |
| return (adreno_dev->gpurev == ADRENO_REV_A225); |
| } |
| |
| static inline int adreno_is_a22x(struct adreno_device *adreno_dev) |
| { |
| return (adreno_dev->gpurev == ADRENO_REV_A220 || |
| adreno_dev->gpurev == ADRENO_REV_A225); |
| } |
| |
| #endif /*__ADRENO_H */ |