msm: clock-8960: Add more gfx3d and vcodec frequencies for 8930ab
On 8930ab, gfx3d and vcodec maximum frequencies have been bumped
to 500MHz and 266MHz respectively. Therefore, update PLL15 frequency
to 1000MHz to support gfx3d clock at 500MHz and also update Fmax
values for both gfx3d and vcodec clocks.
Change-Id: I6296a59fcc67b4edc38834009ce9403df2cf2ab6
Signed-off-by: Seemanta Dutta <seemanta@codeaurora.org>
Signed-off-by: Neha Pandey <nehap@codeaurora.org>
diff --git a/arch/arm/mach-msm/clock-8960.c b/arch/arm/mach-msm/clock-8960.c
index af6ddac..b17918f 100644
--- a/arch/arm/mach-msm/clock-8960.c
+++ b/arch/arm/mach-msm/clock-8960.c
@@ -3556,6 +3556,28 @@
F_END
};
+static struct clk_freq_tbl clk_tbl_gfx3d_8930ab[] = {
+ F_GFX3D( 0, gnd, 0, 0),
+ F_GFX3D( 27000000, pxo, 0, 0),
+ F_GFX3D( 48000000, pll8, 1, 8),
+ F_GFX3D( 54857000, pll8, 1, 7),
+ F_GFX3D( 64000000, pll8, 1, 6),
+ F_GFX3D( 76800000, pll8, 1, 5),
+ F_GFX3D( 96000000, pll8, 1, 4),
+ F_GFX3D(128000000, pll8, 1, 3),
+ F_GFX3D(145455000, pll2, 2, 11),
+ F_GFX3D(160000000, pll2, 1, 5),
+ F_GFX3D(177778000, pll2, 2, 9),
+ F_GFX3D(192000000, pll8, 1, 2),
+ F_GFX3D(200000000, pll2, 1, 4),
+ F_GFX3D(228571000, pll2, 2, 7),
+ F_GFX3D(266667000, pll2, 1, 3),
+ F_GFX3D(320000000, pll2, 2, 5),
+ F_GFX3D(400000000, pll2, 1, 2),
+ F_GFX3D(500000000, pll15, 1, 2),
+ F_END
+};
+
static unsigned long fmax_gfx3d_8064ab[VDD_DIG_NUM] = {
[VDD_DIG_LOW] = 128000000,
[VDD_DIG_NOMINAL] = 325000000,
@@ -3580,6 +3602,12 @@
[VDD_DIG_HIGH] = 450000000
};
+static unsigned long fmax_gfx3d_8930ab[VDD_DIG_NUM] = {
+ [VDD_DIG_LOW] = 192000000,
+ [VDD_DIG_NOMINAL] = 320000000,
+ [VDD_DIG_HIGH] = 500000000
+};
+
static struct bank_masks bmnd_info_gfx3d = {
.bank_sel_mask = BIT(11),
.bank0_mask = {
@@ -4334,6 +4362,12 @@
[VDD_DIG_HIGH] = 266670000,
};
+static unsigned long fmax_vcodec_8930ab[VDD_DIG_NUM] = {
+ [VDD_DIG_LOW] = 100000000,
+ [VDD_DIG_NOMINAL] = 200000000,
+ [VDD_DIG_HIGH] = 266670000
+};
+
#define F_VPE(f, s, d) \
{ \
.freq_hz = f, \
@@ -6501,8 +6535,7 @@
}
/*
- * Program PLL15 to 900MHz with ref clk = 27MHz and
- * only enable PLL main output.
+ * Change PLL15 configuration based on the SoC we're running on.
*/
if (cpu_is_msm8930() || cpu_is_msm8930aa() || cpu_is_msm8627()) {
pll15_config.l = 0x21 | BVAL(31, 7, 0x600);
@@ -6511,6 +6544,13 @@
configure_sr_pll(&pll15_config, &pll15_regs, 0);
/* Disable AUX and BIST outputs */
writel_relaxed(0, MM_PLL3_TEST_CTL_REG);
+ } else if (cpu_is_msm8930ab()) {
+ pll15_config.l = 0x25 | BVAL(31, 7, 0x600);
+ pll15_config.m = 0x25;
+ pll15_config.n = 0x3E7;
+ configure_sr_pll(&pll15_config, &pll15_regs, 0);
+ /* Disable AUX and BIST outputs */
+ writel_relaxed(0, MM_PLL3_TEST_CTL_REG);
}
}
@@ -6590,14 +6630,19 @@
* Change the freq tables and voltage requirements for
* clocks which differ between 8960 and 8930.
*/
- if (cpu_is_msm8930() || cpu_is_msm8627()) {
+ if (cpu_is_msm8930() || cpu_is_msm8627())
gfx3d_clk.c.fmax = fmax_gfx3d_8930;
- } else if (cpu_is_msm8930aa()) {
+ else if (cpu_is_msm8930aa())
gfx3d_clk.c.fmax = fmax_gfx3d_8930aa;
- }
if (cpu_is_msm8930() || cpu_is_msm8930aa() || cpu_is_msm8627()) {
pll15_clk.c.rate = 900000000;
gmem_axi_clk.c.depends = &gfx3d_axi_clk_8930.c;
+ } else if (cpu_is_msm8930ab()) {
+ gfx3d_clk.freq_tbl = clk_tbl_gfx3d_8930ab;
+ pll15_clk.c.rate = 1000000000;
+ gfx3d_clk.c.fmax = fmax_gfx3d_8930ab;
+ gmem_axi_clk.c.depends = &gfx3d_axi_clk_8930.c;
+ vcodec_clk.c.fmax = fmax_vcodec_8930ab;
}
if ((readl_relaxed(PRNG_CLK_NS_REG) & 0x7F) == 0x2B)
prng_clk.freq_tbl = clk_tbl_prng_64;