)]}'
{
  "commit": "aabbaa6036fd847c583f585c6bae82b5a033e6c7",
  "tree": "097a73e1546b7396b49031ab5a3e1d4c1e7c5598",
  "parents": [
    "86028598de16538f02519141756ccf4accfc29a6"
  ],
  "author": {
    "name": "Paul Mackerras",
    "email": "paulus@samba.org",
    "time": "Fri Mar 06 16:27:10 2009 +1100"
  },
  "committer": {
    "name": "Paul Mackerras",
    "email": "paulus@samba.org",
    "time": "Fri Mar 06 16:28:37 2009 +1100"
  },
  "message": "perfcounters/powerpc: add support for POWER5+ processors\n\nImpact: more hardware support\n\nThis adds the back-end for the PMU on the POWER5+ processors (i.e. GS,\nincluding GS DD3 aka POWER5++).  This doesn\u0027t use the fixed-function\nPMC5 and PMC6 since they don\u0027t respect the freeze conditions and don\u0027t\ngenerate interrupts, as on POWER6.\n\nSigned-off-by: Paul Mackerras \u003cpaulus@samba.org\u003e\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "b4c6f466164b64ba6becde7e2bdf91e70963496e",
      "old_mode": 33188,
      "old_path": "arch/powerpc/kernel/Makefile",
      "new_id": "49851e0d8fdeb97c9f8ca85f59991ef620c27459",
      "new_mode": 33188,
      "new_path": "arch/powerpc/kernel/Makefile"
    },
    {
      "type": "modify",
      "old_id": "4fec112386fce8aea04c4c1d92768d007411d36b",
      "old_mode": 33188,
      "old_path": "arch/powerpc/kernel/perf_counter.c",
      "new_id": "162f3981fa27b1dfe5a69cf281593af36e235703",
      "new_mode": 33188,
      "new_path": "arch/powerpc/kernel/perf_counter.c"
    },
    {
      "type": "add",
      "old_id": "0000000000000000000000000000000000000000",
      "old_mode": 0,
      "old_path": "/dev/null",
      "new_id": "cec21ea65b0e2593c29a513e99ec050544989223",
      "new_mode": 33188,
      "new_path": "arch/powerpc/kernel/power5+-pmu.c"
    }
  ]
}