ARM: perf: add support for the Cortex-A5 PMU
This patch adds support for the Cortex-A5 PMU to the ARMv7 perf-event
backend.
Change-Id: Ib8f02b766145cedf59656adcc0cb8fec47bebe6e
Signed-off-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Taniya Das <tdas@codeaurora.org>
diff --git a/arch/arm/kernel/perf_event.c b/arch/arm/kernel/perf_event.c
index c998282..9cb1625 100644
--- a/arch/arm/kernel/perf_event.c
+++ b/arch/arm/kernel/perf_event.c
@@ -680,6 +680,9 @@
case 0xC090: /* Cortex-A9 */
armpmu = armv7_a9_pmu_init();
break;
+ case 0xC050: /* Cortex-A5 */
+ armpmu = armv7_a5_pmu_init();
+ break;
}
/* Intel CPUs [xscale]. */
} else if (0x69 == implementor) {