msm: pil-q6v5-lpass: Enable lpass_q6_axi_clk
This clock must be enabled for the LPASS Q6 to access the memory
from which it will execute.
Change-Id: I1bdd4d8fb32d85c28296de3827f70505be7ee70e
Signed-off-by: Matt Wagantall <mattw@codeaurora.org>
diff --git a/arch/arm/mach-msm/clock-8974.c b/arch/arm/mach-msm/clock-8974.c
index c15370b..d00a25d 100644
--- a/arch/arm/mach-msm/clock-8974.c
+++ b/arch/arm/mach-msm/clock-8974.c
@@ -5033,14 +5033,14 @@
CLK_LOOKUP("core_oe_clk", audio_core_lpaif_pcmoe_clk.c,
"msm-dai-q6.4106"),
- CLK_LOOKUP("core_clk", mss_xo_q6_clk.c, "pil-q6v5-mss"),
- CLK_LOOKUP("bus_clk", mss_bus_q6_clk.c, "pil-q6v5-mss"),
- CLK_LOOKUP("bus_clk", gcc_mss_cfg_ahb_clk.c, ""),
- CLK_LOOKUP("mem_clk", gcc_boot_rom_ahb_clk.c, "pil-q6v5-mss"),
- CLK_LOOKUP("core_clk", q6ss_xo_clk.c, "pil-q6v5-lpass"),
- CLK_LOOKUP("bus_clk", q6ss_ahb_lfabif_clk.c, "pil-q6v5-lpass"),
- CLK_LOOKUP("bus_clk", gcc_lpass_q6_axi_clk.c, ""),
- CLK_LOOKUP("reg_clk", q6ss_ahbm_clk.c, "pil-q6v5-lpass"),
+ CLK_LOOKUP("core_clk", mss_xo_q6_clk.c, "pil-q6v5-mss"),
+ CLK_LOOKUP("bus_clk", mss_bus_q6_clk.c, "pil-q6v5-mss"),
+ CLK_LOOKUP("iface_clk", gcc_mss_cfg_ahb_clk.c, "pil-q6v5-mss"),
+ CLK_LOOKUP("mem_clk", gcc_boot_rom_ahb_clk.c, "pil-q6v5-mss"),
+ CLK_LOOKUP("core_clk", q6ss_xo_clk.c, "pil-q6v5-lpass"),
+ CLK_LOOKUP("bus_clk", gcc_lpass_q6_axi_clk.c, "pil-q6v5-lpass"),
+ CLK_LOOKUP("iface_clk", q6ss_ahb_lfabif_clk.c, "pil-q6v5-lpass"),
+ CLK_LOOKUP("reg_clk", q6ss_ahbm_clk.c, "pil-q6v5-lpass"),
CLK_LOOKUP("core_clk", gcc_prng_ahb_clk.c, "msm_rng"),
CLK_LOOKUP("dfab_clk", pnoc_sps_clk.c, "msm_sps"),
diff --git a/arch/arm/mach-msm/pil-q6v5.c b/arch/arm/mach-msm/pil-q6v5.c
index d8d23c0..1ce73b8 100644
--- a/arch/arm/mach-msm/pil-q6v5.c
+++ b/arch/arm/mach-msm/pil-q6v5.c
@@ -117,9 +117,16 @@
struct q6v5_data *drv = dev_get_drvdata(pil->dev);
int ret;
- ret = clk_prepare_enable(drv->bus_clk);
- if (ret)
- goto err_bus_clk;
+ if (drv->ahb_clk) {
+ ret = clk_prepare_enable(drv->ahb_clk);
+ if (ret)
+ goto err_ahb_clk;
+ }
+ if (drv->axi_clk) {
+ ret = clk_prepare_enable(drv->axi_clk);
+ if (ret)
+ goto err_axi_clk;
+ }
if (drv->ss_clk) {
ret = clk_prepare_enable(drv->ss_clk);
if (ret)
@@ -139,8 +146,10 @@
err_reset:
clk_disable_unprepare(drv->ss_clk);
err_ss_clk:
- clk_disable_unprepare(drv->bus_clk);
-err_bus_clk:
+ clk_disable_unprepare(drv->axi_clk);
+err_axi_clk:
+ clk_disable_unprepare(drv->ahb_clk);
+err_ahb_clk:
return ret;
}
EXPORT_SYMBOL(pil_q6v5_enable_clks);
@@ -152,7 +161,8 @@
clk_disable_unprepare(drv->core_clk);
clk_reset(drv->core_clk, CLK_RESET_ASSERT);
clk_disable_unprepare(drv->ss_clk);
- clk_disable_unprepare(drv->bus_clk);
+ clk_disable_unprepare(drv->axi_clk);
+ clk_disable_unprepare(drv->ahb_clk);
}
EXPORT_SYMBOL(pil_q6v5_disable_clks);
@@ -277,9 +287,13 @@
if (IS_ERR(drv->xo))
return ERR_CAST(drv->xo);
- drv->bus_clk = devm_clk_get(&pdev->dev, "bus_clk");
- if (IS_ERR(drv->bus_clk))
- return ERR_CAST(drv->bus_clk);
+ drv->ahb_clk = devm_clk_get(&pdev->dev, "iface_clk");
+ if (IS_ERR(drv->ahb_clk))
+ return ERR_CAST(drv->ahb_clk);
+
+ drv->axi_clk = devm_clk_get(&pdev->dev, "bus_clk");
+ if (IS_ERR(drv->axi_clk))
+ return ERR_CAST(drv->axi_clk);
drv->core_clk = devm_clk_get(&pdev->dev, "core_clk");
if (IS_ERR(drv->core_clk))
diff --git a/arch/arm/mach-msm/pil-q6v5.h b/arch/arm/mach-msm/pil-q6v5.h
index 6985360..6d08652 100644
--- a/arch/arm/mach-msm/pil-q6v5.h
+++ b/arch/arm/mach-msm/pil-q6v5.h
@@ -22,7 +22,8 @@
struct q6v5_data {
void __iomem *reg_base;
struct clk *xo;
- struct clk *bus_clk;
+ struct clk *ahb_clk;
+ struct clk *axi_clk;
struct clk *core_clk;
struct clk *ss_clk;
void __iomem *axi_halt_base;