)]}'
{
  "commit": "b30c982b23ecb2090b80f0cb7c5af1b458fe1454",
  "tree": "52451203d52f2303ae50ee8ed5f8e5cb05b07bd2",
  "parents": [
    "1de2dfd13d4a4262af6bb6529e3ad88a3e6b4eb4"
  ],
  "author": {
    "name": "Subhash Jadavani",
    "email": "subhashj@codeaurora.org",
    "time": "Tue Mar 27 18:03:16 2012 +0530"
  },
  "committer": {
    "name": "Subhash Jadavani",
    "email": "subhashj@codeaurora.org",
    "time": "Thu Mar 29 00:16:02 2012 +0530"
  },
  "message": "mmc: msm_sdcc: data CRC errors are expected during HS200 tuning\n\nHS200 bus speed mode requires DLL (Delay locked loop) HW block\nto be tuned as clock rate (192 MHz) is greater than 100MHz.\nWhile tuning the DLL block by sending CMD21 for different DLL\nphases, it is quite possible that few CMD21 may fail with data\nCRC errors as clock phase is not correct but these errors are not\nreally worth to be printed out as kernel messages. This change\ndoesn\u0027t allow these errors to be printed.\n\nChange-Id: I5e18b61015f0b3a2478cc2d92e3e1ae5da9eb576\nSigned-off-by: Subhash Jadavani \u003csubhashj@codeaurora.org\u003e\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "e91cf3e3f5c72582a5436324ba6d5f62b6468a8a",
      "old_mode": 33188,
      "old_path": "drivers/mmc/host/msm_sdcc.c",
      "new_id": "69ec6478baa8ddc9e4c1361a6f9a0f85b1069703",
      "new_mode": 33188,
      "new_path": "drivers/mmc/host/msm_sdcc.c"
    }
  ]
}