drivers/net/wireless/ath9k/pci.c - android_kernel_htc_msm8960 - Gitiles

 /*
  * Copyright (c) 2008 Atheros Communications Inc.
  *
  * Permission to use, copy, modify, and/or distribute this software for any
  * purpose with or without fee is hereby granted, provided that the above
  * copyright notice and this permission notice appear in all copies.
  *
  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  */

 #include <linux/nl80211.h>
 #include <linux/pci.h>
 #include "core.h"
 #include "reg.h"
 #include "hw.h"

 static struct pci_device_id ath_pci_id_table[] __devinitdata = {
 	{ PCI_VDEVICE(ATHEROS, 0x0023) }, /* PCI   */
 	{ PCI_VDEVICE(ATHEROS, 0x0024) }, /* PCI-E */
 	{ PCI_VDEVICE(ATHEROS, 0x0027) }, /* PCI   */
 	{ PCI_VDEVICE(ATHEROS, 0x0029) }, /* PCI   */
 	{ PCI_VDEVICE(ATHEROS, 0x002A) }, /* PCI-E */
 	{ PCI_VDEVICE(ATHEROS, 0x002B) }, /* PCI-E */
 	{ 0 }
 };

 /* return bus cachesize in 4B word units */
 static void ath_pci_read_cachesize(struct ath_softc *sc, int *csz)
 {
 	u8 u8tmp;

 	pci_read_config_byte(to_pci_dev(sc->dev), PCI_CACHE_LINE_SIZE,
 			     (u8 *)&u8tmp);
 	*csz = (int)u8tmp;

 	/*
 	 * This check was put in to avoid "unplesant" consequences if
 	 * the bootrom has not fully initialized all PCI devices.
 	 * Sometimes the cache line size register is not set
 	 */

 	if (*csz == 0)
 		*csz = DEFAULT_CACHELINE >> 2;   /* Use the default size */
 }

 static void ath_pci_cleanup(struct ath_softc *sc)
 {
 	struct pci_dev *pdev = to_pci_dev(sc->dev);

 	pci_iounmap(pdev, sc->mem);
 	pci_release_region(pdev, 0);
 	pci_disable_device(pdev);
 }

 static bool ath_pci_eeprom_read(struct ath_hal *ah, u32 off, u16 *data)
 {
 	(void)REG_READ(ah, AR5416_EEPROM_OFFSET + (off << AR5416_EEPROM_S));

 	if (!ath9k_hw_wait(ah,
 			   AR_EEPROM_STATUS_DATA,
 			   AR_EEPROM_STATUS_DATA_BUSY |
 			   AR_EEPROM_STATUS_DATA_PROT_ACCESS, 0)) {
 		return false;
 	}

 	*data = MS(REG_READ(ah, AR_EEPROM_STATUS_DATA),
 		   AR_EEPROM_STATUS_DATA_VAL);

 	return true;
 }

 static struct ath_bus_ops ath_pci_bus_ops = {
 	.read_cachesize = ath_pci_read_cachesize,
 	.cleanup = ath_pci_cleanup,
 	.eeprom_read = ath_pci_eeprom_read,
 };

 static int ath_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
 {
 	void __iomem *mem;
 	struct ath_softc *sc;
 	struct ieee80211_hw *hw;
 	u8 csz;
 	u32 val;
 	int ret = 0;
 	struct ath_hal *ah;

 	if (pci_enable_device(pdev))
 		return -EIO;

 	ret =  pci_set_dma_mask(pdev, DMA_32BIT_MASK);

 	if (ret) {
 		printk(KERN_ERR "ath9k: 32-bit DMA not available\n");
 		goto bad;
 	}

 	ret = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);

 	if (ret) {
 		printk(KERN_ERR "ath9k: 32-bit DMA consistent "
 			"DMA enable failed\n");
 		goto bad;
 	}

 	/*
 	 * Cache line size is used to size and align various
 	 * structures used to communicate with the hardware.
 	 */
 	pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &csz);
 	if (csz == 0) {
 		/*
 		 * Linux 2.4.18 (at least) writes the cache line size
 		 * register as a 16-bit wide register which is wrong.
 		 * We must have this setup properly for rx buffer
 		 * DMA to work so force a reasonable value here if it
 		 * comes up zero.
 		 */
 		csz = L1_CACHE_BYTES / sizeof(u32);
 		pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, csz);
 	}
 	/*
 	 * The default setting of latency timer yields poor results,
 	 * set it to the value used by other systems. It may be worth
 	 * tweaking this setting more.
 	 */
 	pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0xa8);

 	pci_set_master(pdev);

 	/*
 	 * Disable the RETRY_TIMEOUT register (0x41) to keep
 	 * PCI Tx retries from interfering with C3 CPU state.
 	 */
 	pci_read_config_dword(pdev, 0x40, &val);
 	if ((val & 0x0000ff00) != 0)
 		pci_write_config_dword(pdev, 0x40, val & 0xffff00ff);

 	ret = pci_request_region(pdev, 0, "ath9k");
 	if (ret) {
 		dev_err(&pdev->dev, "PCI memory region reserve error\n");
 		ret = -ENODEV;
 		goto bad;
 	}

 	mem = pci_iomap(pdev, 0, 0);
 	if (!mem) {
 		printk(KERN_ERR "PCI memory map error\n") ;
 		ret = -EIO;
 		goto bad1;
 	}

 	hw = ieee80211_alloc_hw(sizeof(struct ath_softc), &ath9k_ops);
 	if (hw == NULL) {
 		printk(KERN_ERR "ath_pci: no memory for ieee80211_hw\n");
 		goto bad2;
 	}

 	SET_IEEE80211_DEV(hw, &pdev->dev);
 	pci_set_drvdata(pdev, hw);

 	sc = hw->priv;
 	sc->hw = hw;
 	sc->dev = &pdev->dev;
 	sc->mem = mem;
 	sc->bus_ops = &ath_pci_bus_ops;

 	if (ath_attach(id->device, sc) != 0) {
 		ret = -ENODEV;
 		goto bad3;
 	}

 	/* setup interrupt service routine */

 	if (request_irq(pdev->irq, ath_isr, IRQF_SHARED, "ath", sc)) {
 		printk(KERN_ERR "%s: request_irq failed\n",
 			wiphy_name(hw->wiphy));
 		ret = -EIO;
 		goto bad4;
 	}

 	sc->irq = pdev->irq;

 	ah = sc->sc_ah;
 	printk(KERN_INFO
 	       "%s: Atheros AR%s MAC/BB Rev:%x "
 	       "AR%s RF Rev:%x: mem=0x%lx, irq=%d\n",
 	       wiphy_name(hw->wiphy),
 	       ath_mac_bb_name(ah->ah_macVersion),
 	       ah->ah_macRev,
 	       ath_rf_name((ah->ah_analog5GhzRev & AR_RADIO_SREV_MAJOR)),
 	       ah->ah_phyRev,
 	       (unsigned long)mem, pdev->irq);

 	return 0;
 bad4:
 	ath_detach(sc);
 bad3:
 	ieee80211_free_hw(hw);
 bad2:
 	pci_iounmap(pdev, mem);
 bad1:
 	pci_release_region(pdev, 0);
 bad:
 	pci_disable_device(pdev);
 	return ret;
 }

 static void ath_pci_remove(struct pci_dev *pdev)
 {
 	struct ieee80211_hw *hw = pci_get_drvdata(pdev);
 	struct ath_softc *sc = hw->priv;

 	ath_cleanup(sc);
 }

 #ifdef CONFIG_PM

 static int ath_pci_suspend(struct pci_dev *pdev, pm_message_t state)
 {
 	struct ieee80211_hw *hw = pci_get_drvdata(pdev);
 	struct ath_softc *sc = hw->priv;

 	ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 1);

 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
 	if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
 		cancel_delayed_work_sync(&sc->rf_kill.rfkill_poll);
 #endif

 	pci_save_state(pdev);
 	pci_disable_device(pdev);
 	pci_set_power_state(pdev, PCI_D3hot);

 	return 0;
 }

 static int ath_pci_resume(struct pci_dev *pdev)
 {
 	struct ieee80211_hw *hw = pci_get_drvdata(pdev);
 	struct ath_softc *sc = hw->priv;
 	u32 val;
 	int err;

 	err = pci_enable_device(pdev);
 	if (err)
 		return err;
 	pci_restore_state(pdev);
 	/*
 	 * Suspend/Resume resets the PCI configuration space, so we have to
 	 * re-disable the RETRY_TIMEOUT register (0x41) to keep
 	 * PCI Tx retries from interfering with C3 CPU state
 	 */
 	pci_read_config_dword(pdev, 0x40, &val);
 	if ((val & 0x0000ff00) != 0)
 		pci_write_config_dword(pdev, 0x40, val & 0xffff00ff);

 	/* Enable LED */
 	ath9k_hw_cfg_output(sc->sc_ah, ATH_LED_PIN,
 			    AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
 	ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 1);

 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
 	/*
 	 * check the h/w rfkill state on resume
 	 * and start the rfkill poll timer
 	 */
 	if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
 		queue_delayed_work(sc->hw->workqueue,
 				   &sc->rf_kill.rfkill_poll, 0);
 #endif

 	return 0;
 }

 #endif /* CONFIG_PM */

 MODULE_DEVICE_TABLE(pci, ath_pci_id_table);

 static struct pci_driver ath_pci_driver = {
 	.name       = "ath9k",
 	.id_table   = ath_pci_id_table,
 	.probe      = ath_pci_probe,
 	.remove     = ath_pci_remove,
 #ifdef CONFIG_PM
 	.suspend    = ath_pci_suspend,
 	.resume     = ath_pci_resume,
 #endif /* CONFIG_PM */
 };

 int __init ath_pci_init(void)
 {
 	return pci_register_driver(&ath_pci_driver);
 }

 void ath_pci_exit(void)
 {
 	pci_unregister_driver(&ath_pci_driver);
 }
	/*
	* Copyright (c) 2008 Atheros Communications Inc.
	*
	* Permission to use, copy, modify, and/or distribute this software for any
	* purpose with or without fee is hereby granted, provided that the above
	* copyright notice and this permission notice appear in all copies.
	*
	* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
	* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
	* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
	* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
	* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
	* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
	* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
	*/

	#include <linux/nl80211.h>
	#include <linux/pci.h>
	#include "core.h"
	#include "reg.h"
	#include "hw.h"

	static struct pci_device_id ath_pci_id_table[] __devinitdata = {
	{ PCI_VDEVICE(ATHEROS, 0x0023) }, /* PCI */
	{ PCI_VDEVICE(ATHEROS, 0x0024) }, /* PCI-E */
	{ PCI_VDEVICE(ATHEROS, 0x0027) }, /* PCI */
	{ PCI_VDEVICE(ATHEROS, 0x0029) }, /* PCI */
	{ PCI_VDEVICE(ATHEROS, 0x002A) }, /* PCI-E */
	{ PCI_VDEVICE(ATHEROS, 0x002B) }, /* PCI-E */
	{ 0 }
	};

	/* return bus cachesize in 4B word units */
	static void ath_pci_read_cachesize(struct ath_softc sc, int csz)
	{
	u8 u8tmp;

	pci_read_config_byte(to_pci_dev(sc->dev), PCI_CACHE_LINE_SIZE,
	(u8 *)&u8tmp);
	*csz = (int)u8tmp;

	/*
	* This check was put in to avoid "unplesant" consequences if
	* the bootrom has not fully initialized all PCI devices.
	* Sometimes the cache line size register is not set
	*/

	if (*csz == 0)
	csz = DEFAULT_CACHELINE >> 2; / Use the default size */
	}

	static void ath_pci_cleanup(struct ath_softc *sc)
	{
	struct pci_dev *pdev = to_pci_dev(sc->dev);

	pci_iounmap(pdev, sc->mem);
	pci_release_region(pdev, 0);
	pci_disable_device(pdev);
	}

	static bool ath_pci_eeprom_read(struct ath_hal ah, u32 off, u16 data)
	{
	(void)REG_READ(ah, AR5416_EEPROM_OFFSET + (off << AR5416_EEPROM_S));

	if (!ath9k_hw_wait(ah,
	AR_EEPROM_STATUS_DATA,
	AR_EEPROM_STATUS_DATA_BUSY \|
	AR_EEPROM_STATUS_DATA_PROT_ACCESS, 0)) {
	return false;
	}

	*data = MS(REG_READ(ah, AR_EEPROM_STATUS_DATA),
	AR_EEPROM_STATUS_DATA_VAL);

	return true;
	}

	static struct ath_bus_ops ath_pci_bus_ops = {
	.read_cachesize = ath_pci_read_cachesize,
	.cleanup = ath_pci_cleanup,
	.eeprom_read = ath_pci_eeprom_read,
	};

	static int ath_pci_probe(struct pci_dev pdev, const struct pci_device_id id)
	{
	void __iomem *mem;
	struct ath_softc *sc;
	struct ieee80211_hw *hw;
	u8 csz;
	u32 val;
	int ret = 0;
	struct ath_hal *ah;

	if (pci_enable_device(pdev))
	return -EIO;

	ret = pci_set_dma_mask(pdev, DMA_32BIT_MASK);

	if (ret) {
	printk(KERN_ERR "ath9k: 32-bit DMA not available\n");
	goto bad;
	}

	ret = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);

	if (ret) {
	printk(KERN_ERR "ath9k: 32-bit DMA consistent "
	"DMA enable failed\n");
	goto bad;
	}

	/*
	* Cache line size is used to size and align various
	* structures used to communicate with the hardware.
	*/
	pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &csz);
	if (csz == 0) {
	/*
	* Linux 2.4.18 (at least) writes the cache line size
	* register as a 16-bit wide register which is wrong.
	* We must have this setup properly for rx buffer
	* DMA to work so force a reasonable value here if it
	* comes up zero.
	*/
	csz = L1_CACHE_BYTES / sizeof(u32);
	pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, csz);
	}
	/*
	* The default setting of latency timer yields poor results,
	* set it to the value used by other systems. It may be worth
	* tweaking this setting more.
	*/
	pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0xa8);

	pci_set_master(pdev);

	/*
	* Disable the RETRY_TIMEOUT register (0x41) to keep
	* PCI Tx retries from interfering with C3 CPU state.
	*/
	pci_read_config_dword(pdev, 0x40, &val);
	if ((val & 0x0000ff00) != 0)
	pci_write_config_dword(pdev, 0x40, val & 0xffff00ff);

	ret = pci_request_region(pdev, 0, "ath9k");
	if (ret) {
	dev_err(&pdev->dev, "PCI memory region reserve error\n");
	ret = -ENODEV;
	goto bad;
	}

	mem = pci_iomap(pdev, 0, 0);
	if (!mem) {
	printk(KERN_ERR "PCI memory map error\n") ;
	ret = -EIO;
	goto bad1;
	}

	hw = ieee80211_alloc_hw(sizeof(struct ath_softc), &ath9k_ops);
	if (hw == NULL) {
	printk(KERN_ERR "ath_pci: no memory for ieee80211_hw\n");
	goto bad2;
	}

	SET_IEEE80211_DEV(hw, &pdev->dev);
	pci_set_drvdata(pdev, hw);

	sc = hw->priv;
	sc->hw = hw;
	sc->dev = &pdev->dev;
	sc->mem = mem;
	sc->bus_ops = &ath_pci_bus_ops;

	if (ath_attach(id->device, sc) != 0) {
	ret = -ENODEV;
	goto bad3;
	}

	/* setup interrupt service routine */

	if (request_irq(pdev->irq, ath_isr, IRQF_SHARED, "ath", sc)) {
	printk(KERN_ERR "%s: request_irq failed\n",
	wiphy_name(hw->wiphy));
	ret = -EIO;
	goto bad4;
	}

	sc->irq = pdev->irq;

	ah = sc->sc_ah;
	printk(KERN_INFO
	"%s: Atheros AR%s MAC/BB Rev:%x "
	"AR%s RF Rev:%x: mem=0x%lx, irq=%d\n",
	wiphy_name(hw->wiphy),
	ath_mac_bb_name(ah->ah_macVersion),
	ah->ah_macRev,
	ath_rf_name((ah->ah_analog5GhzRev & AR_RADIO_SREV_MAJOR)),
	ah->ah_phyRev,
	(unsigned long)mem, pdev->irq);

	return 0;
	bad4:
	ath_detach(sc);
	bad3:
	ieee80211_free_hw(hw);
	bad2:
	pci_iounmap(pdev, mem);
	bad1:
	pci_release_region(pdev, 0);
	bad:
	pci_disable_device(pdev);
	return ret;
	}

	static void ath_pci_remove(struct pci_dev *pdev)
	{
	struct ieee80211_hw *hw = pci_get_drvdata(pdev);
	struct ath_softc *sc = hw->priv;

	ath_cleanup(sc);
	}

	#ifdef CONFIG_PM

	static int ath_pci_suspend(struct pci_dev *pdev, pm_message_t state)
	{
	struct ieee80211_hw *hw = pci_get_drvdata(pdev);
	struct ath_softc *sc = hw->priv;

	ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 1);

	#if defined(CONFIG_RFKILL) \|\| defined(CONFIG_RFKILL_MODULE)
	if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
	cancel_delayed_work_sync(&sc->rf_kill.rfkill_poll);
	#endif

	pci_save_state(pdev);
	pci_disable_device(pdev);
	pci_set_power_state(pdev, PCI_D3hot);

	return 0;
	}

	static int ath_pci_resume(struct pci_dev *pdev)
	{
	struct ieee80211_hw *hw = pci_get_drvdata(pdev);
	struct ath_softc *sc = hw->priv;
	u32 val;
	int err;

	err = pci_enable_device(pdev);
	if (err)
	return err;
	pci_restore_state(pdev);
	/*
	* Suspend/Resume resets the PCI configuration space, so we have to
	* re-disable the RETRY_TIMEOUT register (0x41) to keep
	* PCI Tx retries from interfering with C3 CPU state
	*/
	pci_read_config_dword(pdev, 0x40, &val);
	if ((val & 0x0000ff00) != 0)
	pci_write_config_dword(pdev, 0x40, val & 0xffff00ff);

	/* Enable LED */
	ath9k_hw_cfg_output(sc->sc_ah, ATH_LED_PIN,
	AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
	ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 1);

	#if defined(CONFIG_RFKILL) \|\| defined(CONFIG_RFKILL_MODULE)
	/*
	* check the h/w rfkill state on resume
	* and start the rfkill poll timer
	*/
	if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
	queue_delayed_work(sc->hw->workqueue,
	&sc->rf_kill.rfkill_poll, 0);
	#endif

	return 0;
	}

	#endif /* CONFIG_PM */

	MODULE_DEVICE_TABLE(pci, ath_pci_id_table);

	static struct pci_driver ath_pci_driver = {
	.name = "ath9k",
	.id_table = ath_pci_id_table,
	.probe = ath_pci_probe,
	.remove = ath_pci_remove,
	#ifdef CONFIG_PM
	.suspend = ath_pci_suspend,
	.resume = ath_pci_resume,
	#endif /* CONFIG_PM */
	};

	int __init ath_pci_init(void)
	{
	return pci_register_driver(&ath_pci_driver);
	}

	void ath_pci_exit(void)
	{
	pci_unregister_driver(&ath_pci_driver);
	}