msm: kgsl: Watch SP_FS_FULL_ALU_INSTRUCTIONS for hang detection
Some intensive shader operations can go for the full timeout
in the SP block without changes in th RBBM and CP registers
that we monitor for hang detection. Add the performance counter
SP_FS_FULL_ALU_INSTRUCTIONS to see if any full precision
instructions have been executed during the hang detection interval.
CRs-Fixed: 392730
Change-Id: Ic0dedbadd6e5bcd0b46aab4209430de2f74711f7
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
Signed-off-by: Rajeev Kulkarni <krajeev@codeaurora.org>
diff --git a/drivers/gpu/msm/adreno.c b/drivers/gpu/msm/adreno.c
index 71bd4a2..f394422 100644
--- a/drivers/gpu/msm/adreno.c
+++ b/drivers/gpu/msm/adreno.c
@@ -127,6 +127,8 @@
REG_CP_IB1_BUFSZ,
REG_CP_IB2_BASE,
REG_CP_IB2_BUFSZ,
+ 0,
+ 0
};
const unsigned int hang_detect_regs_count = ARRAY_SIZE(hang_detect_regs);
@@ -1299,6 +1301,12 @@
*/
hang_detect_regs[0] = adreno_dev->gpudev->reg_rbbm_status;
+ /* Add A3XX specific registers for hang detection */
+ if (adreno_is_a3xx(adreno_dev)) {
+ hang_detect_regs[6] = A3XX_RBBM_PERFCTR_SP_7_LO;
+ hang_detect_regs[7] = A3XX_RBBM_PERFCTR_SP_7_HI;
+ }
+
status = kgsl_mmu_start(device);
if (status)
goto error_clk_off;
@@ -2222,6 +2230,10 @@
return 0;
for (i = 0; i < hang_detect_regs_count; i++) {
+
+ if (hang_detect_regs[i] == 0)
+ continue;
+
adreno_regread(device, hang_detect_regs[i],
&curr_reg_val[i]);
if (curr_reg_val[i] != prev_reg_val[i]) {