)]}'
{
  "commit": "b6c7347fffa655a3000d9d41640d222c19fc3065",
  "tree": "ef1789ab0656997f0491e051b92cf833948f2307",
  "parents": [
    "4071c718555d955a35e9651f77086096ad87d498"
  ],
  "author": {
    "name": "Nick Piggin",
    "email": "npiggin@suse.de",
    "time": "Sat Oct 13 03:07:38 2007 +0200"
  },
  "committer": {
    "name": "Linus Torvalds",
    "email": "torvalds@woody.linux-foundation.org",
    "time": "Fri Oct 12 18:41:21 2007 -0700"
  },
  "message": "x86: optimise barriers\n\nAccording to latest memory ordering specification documents from Intel\nand AMD, both manufacturers are committed to in-order loads from\ncacheable memory for the x86 architecture.  Hence, smp_rmb() may be a\nsimple barrier.\n\nAlso according to those documents, and according to existing practice in\nLinux (eg.  spin_unlock doesn\u0027t enforce ordering), stores to cacheable\nmemory are visible in program order too.  Special string stores are safe\n-- their constituent stores may be out of order, but they must complete\nin order WRT surrounding stores.  Nontemporal stores to WB memory can go\nout of order, and so they should be fenced explicitly to make them\nappear in-order WRT other stores.  Hence, smp_wmb() may be a simple\nbarrier.\n\n    http://developer.intel.com/products/processor/manuals/318147.pdf\n    http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/24593.pdf\n\nIn userspace microbenchmarks on a core2 system, fence instructions range\nanywhere from around 15 cycles to 50, which may not be totally\ninsignificant in performance critical paths (code size will go down\ntoo).\n\nHowever the primary motivation for this is to have the canonical barrier\nimplementation for x86 architecture.\n\nsmp_rmb on buggy pentium pros remains a locked op, which is apparently\nrequired.\n\nSigned-off-by: Nick Piggin \u003cnpiggin@suse.de\u003e\nSigned-off-by: Linus Torvalds \u003ctorvalds@linux-foundation.org\u003e\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "8b15bd3057c9b3c4c5ce844e35638396048ab46e",
      "old_mode": 33188,
      "old_path": "include/asm-x86/system_32.h",
      "new_id": "e7e5d426fef58c2b6892fea59c341528d827afaf",
      "new_mode": 33188,
      "new_path": "include/asm-x86/system_32.h"
    },
    {
      "type": "modify",
      "old_id": "eff730b1192682ca85875e909dda13bb1f7e49d9",
      "old_mode": 33188,
      "old_path": "include/asm-x86/system_64.h",
      "new_id": "5022aecc333d7bfe6b24037b3927f15e745e4d7a",
      "new_mode": 33188,
      "new_path": "include/asm-x86/system_64.h"
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}