msm: 8960: add voting for SDCC DFAB clock
SDCC hclk is derived from DFAB (dytona fabric) clock which makes
SDCC hclk rate same as the DFAB clock rate.
SDCC driver should be voting for DFAB clock rate when it's active
(not suspended). This voting is already present for 8660 but missing
on 8960. So this change makes the SDCC driver vote for DFAB clock
rate to be 64MHz when active. If there is no voting in place from SDCC
driver and USB is not connected then DFAB clock runs at 27 MHz.
CRs-fixed: 308068
Signed-off-by: Subhash Jadavani <subhashj@codeaurora.org>
diff --git a/arch/arm/mach-msm/board-msm8960.c b/arch/arm/mach-msm/board-msm8960.c
index 20d63e0..5151d39 100644
--- a/arch/arm/mach-msm/board-msm8960.c
+++ b/arch/arm/mach-msm/board-msm8960.c
@@ -2545,6 +2545,7 @@
#endif
.sup_clk_table = sdc1_sup_clk_rates,
.sup_clk_cnt = ARRAY_SIZE(sdc1_sup_clk_rates),
+ .pclk_src_dfab = 1,
.nonremovable = 1,
.sdcc_v4_sup = true,
.vreg_data = &mmc_slot_vreg_data[SDCC1],
@@ -2558,6 +2559,7 @@
.mmc_bus_width = MMC_CAP_4_BIT_DATA,
.sup_clk_table = sdc3_sup_clk_rates,
.sup_clk_cnt = ARRAY_SIZE(sdc3_sup_clk_rates),
+ .pclk_src_dfab = 1,
#ifdef CONFIG_MMC_MSM_SDC3_WP_SUPPORT
.wpswitch_gpio = PM8921_GPIO_PM_TO_SYS(16),
#endif