msm: pil-q6v5: Disable Q6 core_clk and core_rclk gating
Leaving clock gating enabled for these causes issues for
JTAG debugging. Disable clock gating by default and leave
enabling it again to the Q6 software.
Change-Id: Id6c41b93b94e5fe05a80918aa1e0ce129e857ccc
Signed-off-by: Matt Wagantall <mattw@codeaurora.org>
diff --git a/arch/arm/mach-msm/pil-q6v5.c b/arch/arm/mach-msm/pil-q6v5.c
index a362a7e3..b27d5e5 100644
--- a/arch/arm/mach-msm/pil-q6v5.c
+++ b/arch/arm/mach-msm/pil-q6v5.c
@@ -30,6 +30,7 @@
#define QDSP6SS_RESET 0x014
#define QDSP6SS_GFMUX_CTL 0x020
#define QDSP6SS_PWR_CTL 0x030
+#define QDSP6SS_CGC_OVERRIDE 0x034
/* AXI Halt Register Offsets */
#define AXI_HALTREQ 0x0
@@ -55,6 +56,10 @@
#define Q6SS_CLAMP_IO BIT(20)
#define QDSS_BHS_ON BIT(21)
+/* QDSP6SS_CGC_OVERRIDE */
+#define Q6SS_CORE_CLK_EN BIT(0)
+#define Q6SS_CORE_RCLK_EN BIT(1)
+
int pil_q6v5_make_proxy_votes(struct pil_desc *pil)
{
int ret;
@@ -214,6 +219,11 @@
val = Q6SS_STOP_CORE;
writel_relaxed(val, drv->reg_base + QDSP6SS_RESET);
+ /* Disable clock gating for core and rclk */
+ val = readl_relaxed(drv->reg_base + QDSP6SS_CGC_OVERRIDE);
+ val |= Q6SS_CORE_RCLK_EN | Q6SS_CORE_CLK_EN;
+ writel_relaxed(val, drv->reg_base + QDSP6SS_CGC_OVERRIDE);
+
/* Turn on core clock */
val = readl_relaxed(drv->reg_base + QDSP6SS_GFMUX_CTL);
val |= Q6SS_CLK_ENA;