mmc: msm_sdcc: Reset SPS BAM on error recovery
In the current soft reset sequence performed as part of
CMD/DATA error recovery we do the following:
1) Write 1 to DML_SW_RESET
2) Reset CPSM/DPSM by clearing MCI_CMD and MCI_DATA_CTL
or by writing to MCI_SW_RST_CONFIG.
3) Re-init DML
4) Reconfigure both consumer and producer BAM pipes.
The BAM pipe reset does not reset the sideband signals, since
only SDCC side is reset SDCC - BAM communication will go out
of sync and cause DML to be stuck without transferring data.
Hence reset BAM core every time SDCC is reset (which is on
error recovery).
Fix error handling for sps pipe or device reset.
(cherry picked from commit 3ca90f02963ddbbdb300eb55c49aca18091c3f49)
Change-Id: I82bd6c5f3db6ac71da912cef935dfd179b099ed4
Signed-off-by: Venkat Gopalakrishnan <venkatg@codeaurora.org>
Signed-off-by: Krishna Konda <kkonda@codeaurora.org>
(cherry picked from commit 9b2f00f099f4f17025a9834eb38fc67254164608)
Signed-off-by: Maya Erez <merez@codeaurora.org>
diff --git a/drivers/mmc/host/msm_sdcc.h b/drivers/mmc/host/msm_sdcc.h
index 236785d..d690c7a 100644
--- a/drivers/mmc/host/msm_sdcc.h
+++ b/drivers/mmc/host/msm_sdcc.h
@@ -2,7 +2,7 @@
* linux/drivers/mmc/host/msmsdcc.h - QCT MSM7K SDC Controller
*
* Copyright (C) 2008 Google, All Rights Reserved.
- * Copyright (c) 2009-2012, Code Aurora Forum. All rights reserved.
+ * Copyright (c) 2009-2012, The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
@@ -320,8 +320,7 @@
unsigned int dest_pipe_index;
unsigned int busy;
unsigned int xfer_req_cnt;
- bool pipe_reset_pending;
- bool reset_device;
+ bool reset_bam;
struct tasklet_struct tlet;
};