msm: acpuclock-krait: Remove use of QSB as a CPU or L2 clock source
QSB's rate is tied to the Apps fabric (or BIMC on 8974), which means
that its rate is unpredictable. When the CPU is running at a low
voltage, if the QSB clock source is selected, it's possible that the
CPU clock rate could increase beyond the safe limit for that voltage.
Instead of selecting QSB for power-collapse and hotplug scenarios,
select an always-on source with a predictable rate.
Change-Id: I7c39d443bf49371358d0a618693a6efe2f26fcc4
Signed-off-by: Matt Wagantall <mattw@codeaurora.org>
diff --git a/arch/arm/mach-msm/acpuclock-8064.c b/arch/arm/mach-msm/acpuclock-8064.c
index cf9b877..6f9960d 100644
--- a/arch/arm/mach-msm/acpuclock-8064.c
+++ b/arch/arm/mach-msm/acpuclock-8064.c
@@ -106,102 +106,98 @@
};
static struct l2_level l2_freq_tbl[] __initdata __initdata = {
- [0] = { {STBY_KHZ, QSB, 0, 0, 0x00 }, 1050000, 1050000, 0 },
- [1] = { { 384000, PLL_8, 0, 2, 0x00 }, 1050000, 1050000, 1 },
- [2] = { { 432000, HFPLL, 2, 0, 0x20 }, 1050000, 1050000, 2 },
- [3] = { { 486000, HFPLL, 2, 0, 0x24 }, 1050000, 1050000, 2 },
- [4] = { { 540000, HFPLL, 2, 0, 0x28 }, 1050000, 1050000, 2 },
- [5] = { { 594000, HFPLL, 1, 0, 0x16 }, 1050000, 1050000, 2 },
- [6] = { { 648000, HFPLL, 1, 0, 0x18 }, 1050000, 1050000, 4 },
- [7] = { { 702000, HFPLL, 1, 0, 0x1A }, 1050000, 1050000, 4 },
- [8] = { { 756000, HFPLL, 1, 0, 0x1C }, 1150000, 1150000, 4 },
- [9] = { { 810000, HFPLL, 1, 0, 0x1E }, 1150000, 1150000, 4 },
- [10] = { { 864000, HFPLL, 1, 0, 0x20 }, 1150000, 1150000, 4 },
- [11] = { { 918000, HFPLL, 1, 0, 0x22 }, 1150000, 1150000, 5 },
- [12] = { { 972000, HFPLL, 1, 0, 0x24 }, 1150000, 1150000, 5 },
- [13] = { { 1026000, HFPLL, 1, 0, 0x26 }, 1150000, 1150000, 5 },
- [14] = { { 1080000, HFPLL, 1, 0, 0x28 }, 1150000, 1150000, 5 },
- [15] = { { 1134000, HFPLL, 1, 0, 0x2A }, 1150000, 1150000, 5 },
+ [0] = { { 384000, PLL_8, 0, 2, 0x00 }, 1050000, 1050000, 1 },
+ [1] = { { 432000, HFPLL, 2, 0, 0x20 }, 1050000, 1050000, 2 },
+ [2] = { { 486000, HFPLL, 2, 0, 0x24 }, 1050000, 1050000, 2 },
+ [3] = { { 540000, HFPLL, 2, 0, 0x28 }, 1050000, 1050000, 2 },
+ [4] = { { 594000, HFPLL, 1, 0, 0x16 }, 1050000, 1050000, 2 },
+ [5] = { { 648000, HFPLL, 1, 0, 0x18 }, 1050000, 1050000, 4 },
+ [6] = { { 702000, HFPLL, 1, 0, 0x1A }, 1050000, 1050000, 4 },
+ [7] = { { 756000, HFPLL, 1, 0, 0x1C }, 1150000, 1150000, 4 },
+ [8] = { { 810000, HFPLL, 1, 0, 0x1E }, 1150000, 1150000, 4 },
+ [9] = { { 864000, HFPLL, 1, 0, 0x20 }, 1150000, 1150000, 4 },
+ [10] = { { 918000, HFPLL, 1, 0, 0x22 }, 1150000, 1150000, 5 },
+ [11] = { { 972000, HFPLL, 1, 0, 0x24 }, 1150000, 1150000, 5 },
+ [12] = { { 1026000, HFPLL, 1, 0, 0x26 }, 1150000, 1150000, 5 },
+ [13] = { { 1080000, HFPLL, 1, 0, 0x28 }, 1150000, 1150000, 5 },
+ [14] = { { 1134000, HFPLL, 1, 0, 0x2A }, 1150000, 1150000, 5 },
};
static struct acpu_level acpu_freq_tbl_slow[] __initdata = {
- { 0, { STBY_KHZ, QSB, 0, 0, 0x00 }, L2(0), 950000 },
- { 1, { 384000, PLL_8, 0, 2, 0x00 }, L2(1), 950000 },
- { 0, { 432000, HFPLL, 2, 0, 0x20 }, L2(7), 975000 },
- { 1, { 486000, HFPLL, 2, 0, 0x24 }, L2(7), 975000 },
- { 0, { 540000, HFPLL, 2, 0, 0x28 }, L2(7), 1000000 },
- { 1, { 594000, HFPLL, 1, 0, 0x16 }, L2(7), 1000000 },
- { 0, { 648000, HFPLL, 1, 0, 0x18 }, L2(7), 1025000 },
- { 1, { 702000, HFPLL, 1, 0, 0x1A }, L2(7), 1025000 },
- { 0, { 756000, HFPLL, 1, 0, 0x1C }, L2(7), 1075000 },
- { 1, { 810000, HFPLL, 1, 0, 0x1E }, L2(7), 1075000 },
- { 0, { 864000, HFPLL, 1, 0, 0x20 }, L2(7), 1100000 },
- { 1, { 918000, HFPLL, 1, 0, 0x22 }, L2(7), 1100000 },
- { 0, { 972000, HFPLL, 1, 0, 0x24 }, L2(7), 1125000 },
- { 1, { 1026000, HFPLL, 1, 0, 0x26 }, L2(7), 1125000 },
- { 0, { 1080000, HFPLL, 1, 0, 0x28 }, L2(15), 1175000 },
- { 1, { 1134000, HFPLL, 1, 0, 0x2A }, L2(15), 1175000 },
- { 0, { 1188000, HFPLL, 1, 0, 0x2C }, L2(15), 1200000 },
- { 1, { 1242000, HFPLL, 1, 0, 0x2E }, L2(15), 1200000 },
- { 0, { 1296000, HFPLL, 1, 0, 0x30 }, L2(15), 1225000 },
- { 1, { 1350000, HFPLL, 1, 0, 0x32 }, L2(15), 1225000 },
- { 0, { 1404000, HFPLL, 1, 0, 0x34 }, L2(15), 1237500 },
- { 1, { 1458000, HFPLL, 1, 0, 0x36 }, L2(15), 1237500 },
- { 1, { 1512000, HFPLL, 1, 0, 0x38 }, L2(15), 1250000 },
+ { 1, { 384000, PLL_8, 0, 2, 0x00 }, L2(0), 950000 },
+ { 0, { 432000, HFPLL, 2, 0, 0x20 }, L2(6), 975000 },
+ { 1, { 486000, HFPLL, 2, 0, 0x24 }, L2(6), 975000 },
+ { 0, { 540000, HFPLL, 2, 0, 0x28 }, L2(6), 1000000 },
+ { 1, { 594000, HFPLL, 1, 0, 0x16 }, L2(6), 1000000 },
+ { 0, { 648000, HFPLL, 1, 0, 0x18 }, L2(6), 1025000 },
+ { 1, { 702000, HFPLL, 1, 0, 0x1A }, L2(6), 1025000 },
+ { 0, { 756000, HFPLL, 1, 0, 0x1C }, L2(6), 1075000 },
+ { 1, { 810000, HFPLL, 1, 0, 0x1E }, L2(6), 1075000 },
+ { 0, { 864000, HFPLL, 1, 0, 0x20 }, L2(6), 1100000 },
+ { 1, { 918000, HFPLL, 1, 0, 0x22 }, L2(6), 1100000 },
+ { 0, { 972000, HFPLL, 1, 0, 0x24 }, L2(6), 1125000 },
+ { 1, { 1026000, HFPLL, 1, 0, 0x26 }, L2(6), 1125000 },
+ { 0, { 1080000, HFPLL, 1, 0, 0x28 }, L2(14), 1175000 },
+ { 1, { 1134000, HFPLL, 1, 0, 0x2A }, L2(14), 1175000 },
+ { 0, { 1188000, HFPLL, 1, 0, 0x2C }, L2(14), 1200000 },
+ { 1, { 1242000, HFPLL, 1, 0, 0x2E }, L2(14), 1200000 },
+ { 0, { 1296000, HFPLL, 1, 0, 0x30 }, L2(14), 1225000 },
+ { 1, { 1350000, HFPLL, 1, 0, 0x32 }, L2(14), 1225000 },
+ { 0, { 1404000, HFPLL, 1, 0, 0x34 }, L2(14), 1237500 },
+ { 1, { 1458000, HFPLL, 1, 0, 0x36 }, L2(14), 1237500 },
+ { 1, { 1512000, HFPLL, 1, 0, 0x38 }, L2(14), 1250000 },
{ 0, { 0 } }
};
static struct acpu_level acpu_freq_tbl_nom[] __initdata = {
- { 0, { STBY_KHZ, QSB, 0, 0, 0x00 }, L2(0), 900000 },
- { 1, { 384000, PLL_8, 0, 2, 0x00 }, L2(1), 900000 },
- { 0, { 432000, HFPLL, 2, 0, 0x20 }, L2(7), 925000 },
- { 1, { 486000, HFPLL, 2, 0, 0x24 }, L2(7), 925000 },
- { 0, { 540000, HFPLL, 2, 0, 0x28 }, L2(7), 950000 },
- { 1, { 594000, HFPLL, 1, 0, 0x16 }, L2(7), 950000 },
- { 0, { 648000, HFPLL, 1, 0, 0x18 }, L2(7), 975000 },
- { 1, { 702000, HFPLL, 1, 0, 0x1A }, L2(7), 975000 },
- { 0, { 756000, HFPLL, 1, 0, 0x1C }, L2(7), 1025000 },
- { 1, { 810000, HFPLL, 1, 0, 0x1E }, L2(7), 1025000 },
- { 0, { 864000, HFPLL, 1, 0, 0x20 }, L2(7), 1050000 },
- { 1, { 918000, HFPLL, 1, 0, 0x22 }, L2(7), 1050000 },
- { 0, { 972000, HFPLL, 1, 0, 0x24 }, L2(7), 1075000 },
- { 1, { 1026000, HFPLL, 1, 0, 0x26 }, L2(7), 1075000 },
- { 0, { 1080000, HFPLL, 1, 0, 0x28 }, L2(15), 1125000 },
- { 1, { 1134000, HFPLL, 1, 0, 0x2A }, L2(15), 1125000 },
- { 0, { 1188000, HFPLL, 1, 0, 0x2C }, L2(15), 1150000 },
- { 1, { 1242000, HFPLL, 1, 0, 0x2E }, L2(15), 1150000 },
- { 0, { 1296000, HFPLL, 1, 0, 0x30 }, L2(15), 1175000 },
- { 1, { 1350000, HFPLL, 1, 0, 0x32 }, L2(15), 1175000 },
- { 0, { 1404000, HFPLL, 1, 0, 0x34 }, L2(15), 1187500 },
- { 1, { 1458000, HFPLL, 1, 0, 0x36 }, L2(15), 1187500 },
- { 1, { 1512000, HFPLL, 1, 0, 0x38 }, L2(15), 1200000 },
+ { 1, { 384000, PLL_8, 0, 2, 0x00 }, L2(0), 900000 },
+ { 0, { 432000, HFPLL, 2, 0, 0x20 }, L2(6), 925000 },
+ { 1, { 486000, HFPLL, 2, 0, 0x24 }, L2(6), 925000 },
+ { 0, { 540000, HFPLL, 2, 0, 0x28 }, L2(6), 950000 },
+ { 1, { 594000, HFPLL, 1, 0, 0x16 }, L2(6), 950000 },
+ { 0, { 648000, HFPLL, 1, 0, 0x18 }, L2(6), 975000 },
+ { 1, { 702000, HFPLL, 1, 0, 0x1A }, L2(6), 975000 },
+ { 0, { 756000, HFPLL, 1, 0, 0x1C }, L2(6), 1025000 },
+ { 1, { 810000, HFPLL, 1, 0, 0x1E }, L2(6), 1025000 },
+ { 0, { 864000, HFPLL, 1, 0, 0x20 }, L2(6), 1050000 },
+ { 1, { 918000, HFPLL, 1, 0, 0x22 }, L2(6), 1050000 },
+ { 0, { 972000, HFPLL, 1, 0, 0x24 }, L2(6), 1075000 },
+ { 1, { 1026000, HFPLL, 1, 0, 0x26 }, L2(6), 1075000 },
+ { 0, { 1080000, HFPLL, 1, 0, 0x28 }, L2(14), 1125000 },
+ { 1, { 1134000, HFPLL, 1, 0, 0x2A }, L2(14), 1125000 },
+ { 0, { 1188000, HFPLL, 1, 0, 0x2C }, L2(14), 1150000 },
+ { 1, { 1242000, HFPLL, 1, 0, 0x2E }, L2(14), 1150000 },
+ { 0, { 1296000, HFPLL, 1, 0, 0x30 }, L2(14), 1175000 },
+ { 1, { 1350000, HFPLL, 1, 0, 0x32 }, L2(14), 1175000 },
+ { 0, { 1404000, HFPLL, 1, 0, 0x34 }, L2(14), 1187500 },
+ { 1, { 1458000, HFPLL, 1, 0, 0x36 }, L2(14), 1187500 },
+ { 1, { 1512000, HFPLL, 1, 0, 0x38 }, L2(14), 1200000 },
{ 0, { 0 } }
};
static struct acpu_level acpu_freq_tbl_fast[] __initdata = {
- { 0, { STBY_KHZ, QSB, 0, 0, 0x00 }, L2(0), 850000 },
- { 1, { 384000, PLL_8, 0, 2, 0x00 }, L2(1), 850000 },
- { 0, { 432000, HFPLL, 2, 0, 0x20 }, L2(7), 875000 },
- { 1, { 486000, HFPLL, 2, 0, 0x24 }, L2(7), 875000 },
- { 0, { 540000, HFPLL, 2, 0, 0x28 }, L2(7), 900000 },
- { 1, { 594000, HFPLL, 1, 0, 0x16 }, L2(7), 900000 },
- { 0, { 648000, HFPLL, 1, 0, 0x18 }, L2(7), 925000 },
- { 1, { 702000, HFPLL, 1, 0, 0x1A }, L2(7), 925000 },
- { 0, { 756000, HFPLL, 1, 0, 0x1C }, L2(7), 975000 },
- { 1, { 810000, HFPLL, 1, 0, 0x1E }, L2(7), 975000 },
- { 0, { 864000, HFPLL, 1, 0, 0x20 }, L2(7), 1000000 },
- { 1, { 918000, HFPLL, 1, 0, 0x22 }, L2(7), 1000000 },
- { 0, { 972000, HFPLL, 1, 0, 0x24 }, L2(7), 1025000 },
- { 1, { 1026000, HFPLL, 1, 0, 0x26 }, L2(7), 1025000 },
- { 0, { 1080000, HFPLL, 1, 0, 0x28 }, L2(15), 1075000 },
- { 1, { 1134000, HFPLL, 1, 0, 0x2A }, L2(15), 1075000 },
- { 0, { 1188000, HFPLL, 1, 0, 0x2C }, L2(15), 1100000 },
- { 1, { 1242000, HFPLL, 1, 0, 0x2E }, L2(15), 1100000 },
- { 0, { 1296000, HFPLL, 1, 0, 0x30 }, L2(15), 1125000 },
- { 1, { 1350000, HFPLL, 1, 0, 0x32 }, L2(15), 1125000 },
- { 0, { 1404000, HFPLL, 1, 0, 0x34 }, L2(15), 1137500 },
- { 1, { 1458000, HFPLL, 1, 0, 0x36 }, L2(15), 1137500 },
- { 1, { 1512000, HFPLL, 1, 0, 0x38 }, L2(15), 1150000 },
+ { 1, { 384000, PLL_8, 0, 2, 0x00 }, L2(0), 850000 },
+ { 0, { 432000, HFPLL, 2, 0, 0x20 }, L2(6), 875000 },
+ { 1, { 486000, HFPLL, 2, 0, 0x24 }, L2(6), 875000 },
+ { 0, { 540000, HFPLL, 2, 0, 0x28 }, L2(6), 900000 },
+ { 1, { 594000, HFPLL, 1, 0, 0x16 }, L2(6), 900000 },
+ { 0, { 648000, HFPLL, 1, 0, 0x18 }, L2(6), 925000 },
+ { 1, { 702000, HFPLL, 1, 0, 0x1A }, L2(6), 925000 },
+ { 0, { 756000, HFPLL, 1, 0, 0x1C }, L2(6), 975000 },
+ { 1, { 810000, HFPLL, 1, 0, 0x1E }, L2(6), 975000 },
+ { 0, { 864000, HFPLL, 1, 0, 0x20 }, L2(6), 1000000 },
+ { 1, { 918000, HFPLL, 1, 0, 0x22 }, L2(6), 1000000 },
+ { 0, { 972000, HFPLL, 1, 0, 0x24 }, L2(6), 1025000 },
+ { 1, { 1026000, HFPLL, 1, 0, 0x26 }, L2(6), 1025000 },
+ { 0, { 1080000, HFPLL, 1, 0, 0x28 }, L2(14), 1075000 },
+ { 1, { 1134000, HFPLL, 1, 0, 0x2A }, L2(14), 1075000 },
+ { 0, { 1188000, HFPLL, 1, 0, 0x2C }, L2(14), 1100000 },
+ { 1, { 1242000, HFPLL, 1, 0, 0x2E }, L2(14), 1100000 },
+ { 0, { 1296000, HFPLL, 1, 0, 0x30 }, L2(14), 1125000 },
+ { 1, { 1350000, HFPLL, 1, 0, 0x32 }, L2(14), 1125000 },
+ { 0, { 1404000, HFPLL, 1, 0, 0x34 }, L2(14), 1137500 },
+ { 1, { 1458000, HFPLL, 1, 0, 0x36 }, L2(14), 1137500 },
+ { 1, { 1512000, HFPLL, 1, 0, 0x38 }, L2(14), 1150000 },
{ 0, { 0 } }
};
@@ -222,6 +218,7 @@
.l2_freq_tbl_size = sizeof(l2_freq_tbl),
.bus_scale = &bus_scale_data,
.qfprom_phys_base = 0x00700000,
+ .stby_khz = 384000,
};
static int __init acpuclk_8064_probe(struct platform_device *pdev)