msm: acpuclock-krait: Remove use of QSB as a CPU or L2 clock source
QSB's rate is tied to the Apps fabric (or BIMC on 8974), which means
that its rate is unpredictable. When the CPU is running at a low
voltage, if the QSB clock source is selected, it's possible that the
CPU clock rate could increase beyond the safe limit for that voltage.
Instead of selecting QSB for power-collapse and hotplug scenarios,
select an always-on source with a predictable rate.
Change-Id: I7c39d443bf49371358d0a618693a6efe2f26fcc4
Signed-off-by: Matt Wagantall <mattw@codeaurora.org>
diff --git a/arch/arm/mach-msm/acpuclock-8974.c b/arch/arm/mach-msm/acpuclock-8974.c
index c7800fc..8c89014 100644
--- a/arch/arm/mach-msm/acpuclock-8974.c
+++ b/arch/arm/mach-msm/acpuclock-8974.c
@@ -109,33 +109,31 @@
};
static struct l2_level l2_freq_tbl[] __initdata = {
- [0] = { {STBY_KHZ, QSB, 0, 0, 0 }, LVL_LOW, 1050000, 0 },
- [1] = { { 300000, PLL_0, 0, 2, 0 }, LVL_LOW, 1050000, 2 },
- [2] = { { 384000, HFPLL, 2, 0, 40 }, LVL_NOM, 1050000, 2 },
- [3] = { { 460800, HFPLL, 2, 0, 48 }, LVL_NOM, 1050000, 2 },
- [4] = { { 537600, HFPLL, 1, 0, 28 }, LVL_NOM, 1050000, 2 },
- [5] = { { 576000, HFPLL, 1, 0, 30 }, LVL_NOM, 1050000, 3 },
- [6] = { { 652800, HFPLL, 1, 0, 34 }, LVL_NOM, 1050000, 3 },
- [7] = { { 729600, HFPLL, 1, 0, 38 }, LVL_NOM, 1050000, 3 },
- [8] = { { 806400, HFPLL, 1, 0, 42 }, LVL_NOM, 1050000, 3 },
- [9] = { { 883200, HFPLL, 1, 0, 46 }, LVL_NOM, 1050000, 4 },
- [10] = { { 960000, HFPLL, 1, 0, 50 }, LVL_NOM, 1050000, 4 },
- [11] = { { 1036800, HFPLL, 1, 0, 54 }, LVL_NOM, 1050000, 4 },
+ [0] = { { 300000, PLL_0, 0, 2, 0 }, LVL_LOW, 1050000, 2 },
+ [1] = { { 384000, HFPLL, 2, 0, 40 }, LVL_NOM, 1050000, 2 },
+ [2] = { { 460800, HFPLL, 2, 0, 48 }, LVL_NOM, 1050000, 2 },
+ [3] = { { 537600, HFPLL, 1, 0, 28 }, LVL_NOM, 1050000, 2 },
+ [4] = { { 576000, HFPLL, 1, 0, 30 }, LVL_NOM, 1050000, 3 },
+ [5] = { { 652800, HFPLL, 1, 0, 34 }, LVL_NOM, 1050000, 3 },
+ [6] = { { 729600, HFPLL, 1, 0, 38 }, LVL_NOM, 1050000, 3 },
+ [7] = { { 806400, HFPLL, 1, 0, 42 }, LVL_NOM, 1050000, 3 },
+ [8] = { { 883200, HFPLL, 1, 0, 46 }, LVL_NOM, 1050000, 4 },
+ [9] = { { 960000, HFPLL, 1, 0, 50 }, LVL_NOM, 1050000, 4 },
+ [10] = { { 1036800, HFPLL, 1, 0, 54 }, LVL_NOM, 1050000, 4 },
};
static struct acpu_level acpu_freq_tbl[] __initdata = {
- { 0, {STBY_KHZ, QSB, 0, 0, 0 }, L2(0), 1050000, 3200000 },
- { 1, { 300000, PLL_0, 0, 2, 0 }, L2(1), 1050000, 3200000 },
- { 1, { 384000, HFPLL, 2, 0, 40 }, L2(2), 1050000, 3200000 },
- { 1, { 460800, HFPLL, 2, 0, 48 }, L2(3), 1050000, 3200000 },
- { 1, { 537600, HFPLL, 1, 0, 28 }, L2(4), 1050000, 3200000 },
- { 1, { 576000, HFPLL, 1, 0, 30 }, L2(5), 1050000, 3200000 },
- { 1, { 652800, HFPLL, 1, 0, 34 }, L2(6), 1050000, 3200000 },
- { 1, { 729600, HFPLL, 1, 0, 38 }, L2(7), 1050000, 3200000 },
- { 1, { 806400, HFPLL, 1, 0, 42 }, L2(8), 1050000, 3200000 },
- { 1, { 883200, HFPLL, 1, 0, 46 }, L2(9), 1050000, 3200000 },
- { 1, { 960000, HFPLL, 1, 0, 50 }, L2(10), 1050000, 3200000 },
- { 1, { 1036800, HFPLL, 1, 0, 54 }, L2(11), 1050000, 3200000 },
+ { 1, { 300000, PLL_0, 0, 2, 0 }, L2(0), 1050000, 3200000 },
+ { 1, { 384000, HFPLL, 2, 0, 40 }, L2(1), 1050000, 3200000 },
+ { 1, { 460800, HFPLL, 2, 0, 48 }, L2(2), 1050000, 3200000 },
+ { 1, { 537600, HFPLL, 1, 0, 28 }, L2(3), 1050000, 3200000 },
+ { 1, { 576000, HFPLL, 1, 0, 30 }, L2(4), 1050000, 3200000 },
+ { 1, { 652800, HFPLL, 1, 0, 34 }, L2(5), 1050000, 3200000 },
+ { 1, { 729600, HFPLL, 1, 0, 38 }, L2(6), 1050000, 3200000 },
+ { 1, { 806400, HFPLL, 1, 0, 42 }, L2(7), 1050000, 3200000 },
+ { 1, { 883200, HFPLL, 1, 0, 46 }, L2(8), 1050000, 3200000 },
+ { 1, { 960000, HFPLL, 1, 0, 50 }, L2(9), 1050000, 3200000 },
+ { 1, { 1036800, HFPLL, 1, 0, 54 }, L2(10), 1050000, 3200000 },
{ 0, { 0 } }
};
@@ -154,6 +152,7 @@
.l2_freq_tbl_size = sizeof(l2_freq_tbl),
.bus_scale = &bus_scale_data,
.qfprom_phys_base = 0xFC4A8000,
+ .stby_khz = 300000,
};
static int __init acpuclk_8974_probe(struct platform_device *pdev)