)]}'
{
  "commit": "b7ec479553b8755dd95ee988a957cbf2aef351dc",
  "tree": "b2066a113c7e0bb1546564038c692f6f423315bf",
  "parents": [
    "7240f1f183f085f6b7af44ec274b5b6123dfdead"
  ],
  "author": {
    "name": "Nicolas Pitre",
    "email": "nico@cam.org",
    "time": "Sun Nov 06 14:42:37 2005 +0000"
  },
  "committer": {
    "name": "Russell King",
    "email": "rmk+kernel@arm.linux.org.uk",
    "time": "Sun Nov 06 14:42:37 2005 +0000"
  },
  "message": "[ARM] 3115/1: small optimizations to exception vector entry code\n\nPatch from Nicolas Pitre\n\nSince we know the value of cpsr on entry, we can replace the bic+orr with\na single eor.  Also remove a possible result delay (at least on XScale).\n\nSigned-off-by: Nicolas Pitre \u003cnico@cam.org\u003e\nSigned-off-by: Russell King \u003crmk+kernel@arm.linux.org.uk\u003e\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "be439cab92c62dcf2e58aac391ea99b99e0efe01",
      "old_mode": 33188,
      "old_path": "arch/arm/kernel/entry-armv.S",
      "new_id": "a511ec5b11a33344c945b66811b889c0a91bf084",
      "new_mode": 33188,
      "new_path": "arch/arm/kernel/entry-armv.S"
    }
  ]
}